drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

   1 #ifndef __NVKM_BUS_HWSQ_H__
   2 #define __NVKM_BUS_HWSQ_H__
   3 #include <subdev/bus.h>
   4
   5 struct hwsq {
   6         struct nvkm_subdev *subdev;
   7         struct nvkm_hwsq *hwsq;
   8         int sequence;
   9 };
  10
  11 struct hwsq_reg {
  12         int sequence;
  13         bool force;
  14         u32 addr[2];
  15         u32 data;
  16 };
  17
  18 static inline struct hwsq_reg
  19 hwsq_reg2(u32 addr1, u32 addr2)
  20 {
  21         return (struct hwsq_reg) {
  22                 .sequence = 0,
  23                 .force = 0,
  24                 .addr = { addr1, addr2 },
  25                 .data = 0xdeadbeef,
  26         };
  27 }
  28
  29 static inline struct hwsq_reg
  30 hwsq_reg(u32 addr)
  31 {
  32         return hwsq_reg2(addr, addr);
  33 }
  34
  35 static inline int
  36 hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
  37 {
  38         struct nvkm_bus *pbus = nvkm_bus(subdev);
  39         int ret;
  40
  41         ret = nvkm_hwsq_init(pbus, &ram->hwsq);
  42         if (ret)
  43                 return ret;
  44
  45         ram->sequence++;
  46         ram->subdev = subdev;
  47         return 0;
  48 }
  49
  50 static inline int
  51 hwsq_exec(struct hwsq *ram, bool exec)
  52 {
  53         int ret = 0;
  54         if (ram->subdev) {
  55                 ret = nvkm_hwsq_fini(&ram->hwsq, exec);
  56                 ram->subdev = NULL;
  57         }
  58         return ret;
  59 }
  60
  61 static inline u32
  62 hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)
  63 {
  64         if (reg->sequence != ram->sequence)
  65                 reg->data = nv_rd32(ram->subdev, reg->addr[0]);
  66         return reg->data;
  67 }
  68
  69 static inline void
  70 hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
  71 {
  72         reg->sequence = ram->sequence;
  73         reg->data = data;
  74         if (reg->addr[0] != reg->addr[1])
  75                 nvkm_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
  76         nvkm_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
  77 }
  78
  79 static inline void
  80 hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg)
  81 {
  82         reg->force = true;
  83 }
  84
  85 static inline u32
  86 hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
  87 {
  88         u32 temp = hwsq_rd32(ram, reg);
  89         if (temp != ((temp & ~mask) | data) || reg->force)
  90                 hwsq_wr32(ram, reg, (temp & ~mask) | data);
  91         return temp;
  92 }
  93
  94 static inline void
  95 hwsq_setf(struct hwsq *ram, u8 flag, int data)
  96 {
  97         nvkm_hwsq_setf(ram->hwsq, flag, data);
  98 }
  99
 100 static inline void
 101 hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
 102 {
 103         nvkm_hwsq_wait(ram->hwsq, flag, data);
 104 }
 105
 106 static inline void
 107 hwsq_nsec(struct hwsq *ram, u32 nsec)
 108 {
 109         nvkm_hwsq_nsec(ram->hwsq, nsec);
 110 }
 111 #endif