drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c

   1 /*
   2  * Copyright 2012 Nouveau Community
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Martin Peres <martin.peres@labri.fr>
  23  *          Ben Skeggs
  24  */
  25 #include "nv04.h"
  26
  27 #include <subdev/timer.h>
  28
  29 static int
  30 nv50_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
  31 {
  32         struct nv50_bus_priv *priv = (void *)pbus;
  33         int i;
  34
  35         nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
  36         nv_wr32(pbus, 0x001304, 0x00000000);
  37         for (i = 0; i < size; i++)
  38                 nv_wr32(priv, 0x001400 + (i * 4), data[i]);
  39         nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
  40         nv_wr32(pbus, 0x00130c, 0x00000003);
  41
  42         return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
  43 }
  44
  45 void
  46 nv50_bus_intr(struct nvkm_subdev *subdev)
  47 {
  48         struct nvkm_bus *pbus = nvkm_bus(subdev);
  49         u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
  50
  51         if (stat & 0x00000008) {
  52                 u32 addr = nv_rd32(pbus, 0x009084);
  53                 u32 data = nv_rd32(pbus, 0x009088);
  54
  55                 nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
  56                          (addr & 0x00000002) ? "write" : "read", data,
  57                          (addr & 0x00fffffc));
  58
  59                 stat &= ~0x00000008;
  60                 nv_wr32(pbus, 0x001100, 0x00000008);
  61         }
  62
  63         if (stat & 0x00010000) {
  64                 subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
  65                 if (subdev && subdev->intr)
  66                         subdev->intr(subdev);
  67                 stat &= ~0x00010000;
  68                 nv_wr32(pbus, 0x001100, 0x00010000);
  69         }
  70
  71         if (stat) {
  72                 nv_error(pbus, "unknown intr 0x%08x\n", stat);
  73                 nv_mask(pbus, 0x001140, stat, 0);
  74         }
  75 }
  76
  77 int
  78 nv50_bus_init(struct nvkm_object *object)
  79 {
  80         struct nv04_bus_priv *priv = (void *)object;
  81         int ret;
  82
  83         ret = nvkm_bus_init(&priv->base);
  84         if (ret)
  85                 return ret;
  86
  87         nv_wr32(priv, 0x001100, 0xffffffff);
  88         nv_wr32(priv, 0x001140, 0x00010008);
  89         return 0;
  90 }
  91
  92 struct nvkm_oclass *
  93 nv50_bus_oclass = &(struct nv04_bus_impl) {
  94         .base.handle = NV_SUBDEV(BUS, 0x50),
  95         .base.ofuncs = &(struct nvkm_ofuncs) {
  96                 .ctor = nv04_bus_ctor,
  97                 .dtor = _nvkm_bus_dtor,
  98                 .init = nv50_bus_init,
  99                 .fini = _nvkm_bus_fini,
 100         },
 101         .intr = nv50_bus_intr,
 102         .hwsq_exec = nv50_bus_hwsq_exec,
 103         .hwsq_size = 64,
 104 }.base;