drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

   1 /*
   2  * Copyright (C) 2010 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26 #include "nv04.h"
  27
  28 void
  29 nv20_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
  30                   u32 flags, struct nvkm_fb_tile *tile)
  31 {
  32         tile->addr  = 0x00000001 | addr;
  33         tile->limit = max(1u, addr + size) - 1;
  34         tile->pitch = pitch;
  35         if (flags & 4) {
  36                 pfb->tile.comp(pfb, i, size, flags, tile);
  37                 tile->addr |= 2;
  38         }
  39 }
  40
  41 static void
  42 nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
  43                   struct nvkm_fb_tile *tile)
  44 {
  45         u32 tiles = DIV_ROUND_UP(size, 0x40);
  46         u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
  47         if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
  48                 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */
  49                 else              tile->zcomp = 0x04000000; /* Z24S8 */
  50                 tile->zcomp |= tile->tag->offset;
  51                 tile->zcomp |= 0x80000000; /* enable */
  52 #ifdef __BIG_ENDIAN
  53                 tile->zcomp |= 0x08000000;
  54 #endif
  55         }
  56 }
  57
  58 void
  59 nv20_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
  60 {
  61         tile->addr  = 0;
  62         tile->limit = 0;
  63         tile->pitch = 0;
  64         tile->zcomp = 0;
  65         nvkm_mm_free(&pfb->tags, &tile->tag);
  66 }
  67
  68 void
  69 nv20_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
  70 {
  71         nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
  72         nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
  73         nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
  74         nv_rd32(pfb, 0x100240 + (i * 0x10));
  75         nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp);
  76 }
  77
  78 struct nvkm_oclass *
  79 nv20_fb_oclass = &(struct nv04_fb_impl) {
  80         .base.base.handle = NV_SUBDEV(FB, 0x20),
  81         .base.base.ofuncs = &(struct nvkm_ofuncs) {
  82                 .ctor = nv04_fb_ctor,
  83                 .dtor = _nvkm_fb_dtor,
  84                 .init = _nvkm_fb_init,
  85                 .fini = _nvkm_fb_fini,
  86         },
  87         .base.memtype = nv04_fb_memtype_valid,
  88         .base.ram = &nv20_ram_oclass,
  89         .tile.regions = 8,
  90         .tile.init = nv20_fb_tile_init,
  91         .tile.comp = nv20_fb_tile_comp,
  92         .tile.fini = nv20_fb_tile_fini,
  93         .tile.prog = nv20_fb_tile_prog,
  94 }.base.base;