ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / subdev / fb / nv40.c
blobdbe5c1910c2c1ea8dfa8ea33124a44c0ce7d0e9b
1 /*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "nv04.h"
28 void
29 nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags,
30 struct nvkm_fb_tile *tile)
32 u32 tiles = DIV_ROUND_UP(size, 0x80);
33 u32 tags = round_up(tiles / pfb->ram->parts, 0x100);
34 if ( (flags & 2) &&
35 !nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
36 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */
37 tile->zcomp |= ((tile->tag->offset ) >> 8);
38 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
39 #ifdef __BIG_ENDIAN
40 tile->zcomp |= 0x40000000;
41 #endif
45 static int
46 nv40_fb_init(struct nvkm_object *object)
48 struct nv04_fb_priv *priv = (void *)object;
49 int ret;
51 ret = nvkm_fb_init(&priv->base);
52 if (ret)
53 return ret;
55 nv_mask(priv, 0x10033c, 0x00008000, 0x00000000);
56 return 0;
59 struct nvkm_oclass *
60 nv40_fb_oclass = &(struct nv04_fb_impl) {
61 .base.base.handle = NV_SUBDEV(FB, 0x40),
62 .base.base.ofuncs = &(struct nvkm_ofuncs) {
63 .ctor = nv04_fb_ctor,
64 .dtor = _nvkm_fb_dtor,
65 .init = nv40_fb_init,
66 .fini = _nvkm_fb_fini,
68 .base.memtype = nv04_fb_memtype_valid,
69 .base.ram = &nv40_ram_oclass,
70 .tile.regions = 8,
71 .tile.init = nv30_fb_tile_init,
72 .tile.comp = nv40_fb_tile_comp,
73 .tile.fini = nv20_fb_tile_fini,
74 .tile.prog = nv20_fb_tile_prog,
75 }.base.base;