drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

   1 /*
   2  * Copyright (C) 2010 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26 #include "nv04.h"
  27
  28 void
  29 nv41_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
  30 {
  31         nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
  32         nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
  33         nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
  34         nv_rd32(pfb, 0x100600 + (i * 0x10));
  35         nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp);
  36 }
  37
  38 int
  39 nv41_fb_init(struct nvkm_object *object)
  40 {
  41         struct nv04_fb_priv *priv = (void *)object;
  42         int ret;
  43
  44         ret = nvkm_fb_init(&priv->base);
  45         if (ret)
  46                 return ret;
  47
  48         nv_wr32(priv, 0x100800, 0x00000001);
  49         return 0;
  50 }
  51
  52 struct nvkm_oclass *
  53 nv41_fb_oclass = &(struct nv04_fb_impl) {
  54         .base.base.handle = NV_SUBDEV(FB, 0x41),
  55         .base.base.ofuncs = &(struct nvkm_ofuncs) {
  56                 .ctor = nv04_fb_ctor,
  57                 .dtor = _nvkm_fb_dtor,
  58                 .init = nv41_fb_init,
  59                 .fini = _nvkm_fb_fini,
  60         },
  61         .base.memtype = nv04_fb_memtype_valid,
  62         .base.ram = &nv41_ram_oclass,
  63         .tile.regions = 12,
  64         .tile.init = nv30_fb_tile_init,
  65         .tile.comp = nv40_fb_tile_comp,
  66         .tile.fini = nv20_fb_tile_fini,
  67         .tile.prog = nv41_fb_tile_prog,
  68 }.base.base;