drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

   1 /*
   2  * Copyright (C) 2010 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26 #include "nv04.h"
  27
  28 static void
  29 nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
  30                   u32 flags, struct nvkm_fb_tile *tile)
  31 {
  32         tile->addr  = 0x00000001; /* mode = vram */
  33         tile->addr |= addr;
  34         tile->limit = max(1u, addr + size) - 1;
  35         tile->pitch = pitch;
  36 }
  37
  38 void
  39 nv44_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
  40 {
  41         nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
  42         nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
  43         nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
  44         nv_rd32(pfb, 0x100600 + (i * 0x10));
  45 }
  46
  47 int
  48 nv44_fb_init(struct nvkm_object *object)
  49 {
  50         struct nv04_fb_priv *priv = (void *)object;
  51         int ret;
  52
  53         ret = nvkm_fb_init(&priv->base);
  54         if (ret)
  55                 return ret;
  56
  57         nv_wr32(priv, 0x100850, 0x80000000);
  58         nv_wr32(priv, 0x100800, 0x00000001);
  59         return 0;
  60 }
  61
  62 struct nvkm_oclass *
  63 nv44_fb_oclass = &(struct nv04_fb_impl) {
  64         .base.base.handle = NV_SUBDEV(FB, 0x44),
  65         .base.base.ofuncs = &(struct nvkm_ofuncs) {
  66                 .ctor = nv04_fb_ctor,
  67                 .dtor = _nvkm_fb_dtor,
  68                 .init = nv44_fb_init,
  69                 .fini = _nvkm_fb_fini,
  70         },
  71         .base.memtype = nv04_fb_memtype_valid,
  72         .base.ram = &nv44_ram_oclass,
  73         .tile.regions = 12,
  74         .tile.init = nv44_fb_tile_init,
  75         .tile.fini = nv20_fb_tile_fini,
  76         .tile.prog = nv44_fb_tile_prog,
  77 }.base.base;