drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c

   1 /*
   2  * Copyright (C) 2010 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26 #include "nv04.h"
  27
  28 void
  29 nv46_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
  30                   u32 flags, struct nvkm_fb_tile *tile)
  31 {
  32         /* for performance, select alternate bank offset for zeta */
  33         if (!(flags & 4)) tile->addr = (0 << 3);
  34         else              tile->addr = (1 << 3);
  35
  36         tile->addr |= 0x00000001; /* mode = vram */
  37         tile->addr |= addr;
  38         tile->limit = max(1u, addr + size) - 1;
  39         tile->pitch = pitch;
  40 }
  41
  42 struct nvkm_oclass *
  43 nv46_fb_oclass = &(struct nv04_fb_impl) {
  44         .base.base.handle = NV_SUBDEV(FB, 0x46),
  45         .base.base.ofuncs = &(struct nvkm_ofuncs) {
  46                 .ctor = nv04_fb_ctor,
  47                 .dtor = _nvkm_fb_dtor,
  48                 .init = nv44_fb_init,
  49                 .fini = _nvkm_fb_fini,
  50         },
  51         .base.memtype = nv04_fb_memtype_valid,
  52         .base.ram = &nv44_ram_oclass,
  53         .tile.regions = 15,
  54         .tile.init = nv46_fb_tile_init,
  55         .tile.fini = nv20_fb_tile_fini,
  56         .tile.prog = nv44_fb_tile_prog,
  57 }.base.base;