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ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / subdev / fb / ramgk104.c
blob1ef15c3e6a81bed1ccb8e44ad76359f90361e1e2
1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "ramfuc.h"
25 #include "gf100.h"
26
27 #include <core/device.h>
28 #include <core/option.h>
29 #include <subdev/bios.h>
30 #include <subdev/bios/init.h>
31 #include <subdev/bios/M0205.h>
32 #include <subdev/bios/M0209.h>
33 #include <subdev/bios/pll.h>
34 #include <subdev/bios/rammap.h>
35 #include <subdev/bios/timing.h>
36 #include <subdev/clk.h>
37 #include <subdev/clk/pll.h>
38 #include <subdev/gpio.h>
39
40 struct gk104_ramfuc {
41 struct ramfuc base;
42
43 struct nvbios_pll refpll;
44 struct nvbios_pll mempll;
45
46 struct ramfuc_reg r_gpioMV;
47 u32 r_funcMV[2];
48 struct ramfuc_reg r_gpio2E;
49 u32 r_func2E[2];
50 struct ramfuc_reg r_gpiotrig;
51
52 struct ramfuc_reg r_0x132020;
53 struct ramfuc_reg r_0x132028;
54 struct ramfuc_reg r_0x132024;
55 struct ramfuc_reg r_0x132030;
56 struct ramfuc_reg r_0x132034;
57 struct ramfuc_reg r_0x132000;
58 struct ramfuc_reg r_0x132004;
59 struct ramfuc_reg r_0x132040;
60
61 struct ramfuc_reg r_0x10f248;
62 struct ramfuc_reg r_0x10f290;
63 struct ramfuc_reg r_0x10f294;
64 struct ramfuc_reg r_0x10f298;
65 struct ramfuc_reg r_0x10f29c;
66 struct ramfuc_reg r_0x10f2a0;
67 struct ramfuc_reg r_0x10f2a4;
68 struct ramfuc_reg r_0x10f2a8;
69 struct ramfuc_reg r_0x10f2ac;
70 struct ramfuc_reg r_0x10f2cc;
71 struct ramfuc_reg r_0x10f2e8;
72 struct ramfuc_reg r_0x10f250;
73 struct ramfuc_reg r_0x10f24c;
74 struct ramfuc_reg r_0x10fec4;
75 struct ramfuc_reg r_0x10fec8;
76 struct ramfuc_reg r_0x10f604;
77 struct ramfuc_reg r_0x10f614;
78 struct ramfuc_reg r_0x10f610;
79 struct ramfuc_reg r_0x100770;
80 struct ramfuc_reg r_0x100778;
81 struct ramfuc_reg r_0x10f224;
82
83 struct ramfuc_reg r_0x10f870;
84 struct ramfuc_reg r_0x10f698;
85 struct ramfuc_reg r_0x10f694;
86 struct ramfuc_reg r_0x10f6b8;
87 struct ramfuc_reg r_0x10f808;
88 struct ramfuc_reg r_0x10f670;
89 struct ramfuc_reg r_0x10f60c;
90 struct ramfuc_reg r_0x10f830;
91 struct ramfuc_reg r_0x1373ec;
92 struct ramfuc_reg r_0x10f800;
93 struct ramfuc_reg r_0x10f82c;
94
95 struct ramfuc_reg r_0x10f978;
96 struct ramfuc_reg r_0x10f910;
97 struct ramfuc_reg r_0x10f914;
98
99 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
100
101 struct ramfuc_reg r_0x62c000;
102
103 struct ramfuc_reg r_0x10f200;
104
105 struct ramfuc_reg r_0x10f210;
106 struct ramfuc_reg r_0x10f310;
107 struct ramfuc_reg r_0x10f314;
108 struct ramfuc_reg r_0x10f318;
109 struct ramfuc_reg r_0x10f090;
110 struct ramfuc_reg r_0x10f69c;
111 struct ramfuc_reg r_0x10f824;
112 struct ramfuc_reg r_0x1373f0;
113 struct ramfuc_reg r_0x1373f4;
114 struct ramfuc_reg r_0x137320;
115 struct ramfuc_reg r_0x10f65c;
116 struct ramfuc_reg r_0x10f6bc;
117 struct ramfuc_reg r_0x100710;
118 struct ramfuc_reg r_0x100750;
119 };
120
121 struct gk104_ram {
122 struct nvkm_ram base;
123 struct gk104_ramfuc fuc;
124
125 struct list_head cfg;
126 u32 parts;
127 u32 pmask;
128 u32 pnuts;
129
130 struct nvbios_ramcfg diff;
131 int from;
132 int mode;
133 int N1, fN1, M1, P1;
134 int N2, M2, P2;
135 };
136
137 /*******************************************************************************
138 * GDDR5
139 ******************************************************************************/
140 static void
141 gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data)
142 {
143 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
144 u32 addr = 0x110974, i;
145
146 ram_mask(fuc, 0x10f910, mask, data);
147 ram_mask(fuc, 0x10f914, mask, data);
148
149 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
150 if (ram->pmask & (1 << i))
151 continue;
152 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
153 }
154 }
155
156 static void
157 r1373f4_init(struct gk104_ramfuc *fuc)
158 {
159 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
162 const u32 runk0 = ram->fN1 << 16;
163 const u32 runk1 = ram->fN1;
164
165 if (ram->from == 2) {
166 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
167 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
168 } else {
169 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
170 }
171
172 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
173 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
174
175 /* (re)program refpll, if required */
176 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
177 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
178 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
179 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
180 ram_wr32(fuc, 0x137320, 0x00000000);
181 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
182 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
183 ram_wr32(fuc, 0x132024, rcoef);
184 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
185 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
186 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
187 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
188 }
189
190 /* (re)program mempll, if required */
191 if (ram->mode == 2) {
192 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
193 ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
194 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
195 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
196 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
197 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
198 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
199 } else {
200 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
201 }
202
203 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
204 }
205
206 static void
207 r1373f4_fini(struct gk104_ramfuc *fuc)
208 {
209 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
210 struct nvkm_ram_data *next = ram->base.next;
211 u8 v0 = next->bios.ramcfg_11_03_c0;
212 u8 v1 = next->bios.ramcfg_11_03_30;
213 u32 tmp;
214
215 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
216 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
217 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
218 if (ram->mode == 2) {
219 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
220 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
221 } else {
222 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
223 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
224 }
225 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
226 }
227
228 static void
229 gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
230 u32 _mask, u32 _data, u32 _copy)
231 {
232 struct gk104_fb_priv *priv = (void *)nvkm_fb(ram);
233 struct ramfuc *fuc = &ram->fuc.base;
234 u32 addr = 0x110000 + (reg->addr & 0xfff);
235 u32 mask = _mask | _copy;
236 u32 data = (_data & _mask) | (reg->data & _copy);
237 u32 i;
238
239 for (i = 0; i < 16; i++, addr += 0x1000) {
240 if (ram->pnuts & (1 << i)) {
241 u32 prev = nv_rd32(priv, addr);
242 u32 next = (prev & ~mask) | data;
243 nvkm_memx_wr32(fuc->memx, addr, next);
244 }
245 }
246 }
247 #define ram_nuts(s,r,m,d,c) \
248 gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
249
250 static int
251 gk104_ram_calc_gddr5(struct nvkm_fb *pfb, u32 freq)
252 {
253 struct gk104_ram *ram = (void *)pfb->ram;
254 struct gk104_ramfuc *fuc = &ram->fuc;
255 struct nvkm_ram_data *next = ram->base.next;
256 int vc = !next->bios.ramcfg_11_02_08;
257 int mv = !next->bios.ramcfg_11_02_04;
258 u32 mask, data;
259
260 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
261 ram_block(fuc);
262 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
263
264 /* MR1: turn termination on early, for some reason.. */
265 if ((ram->base.mr[1] & 0x03c) != 0x030) {
266 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
267 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
268 }
269
270 if (vc == 1 && ram_have(fuc, gpio2E)) {
271 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
272 if (temp != ram_rd32(fuc, gpio2E)) {
273 ram_wr32(fuc, gpiotrig, 1);
274 ram_nsec(fuc, 20000);
275 }
276 }
277
278 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
279
280 gk104_ram_train(fuc, 0x01020000, 0x000c0000);
281
282 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
283 ram_nsec(fuc, 1000);
284 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
285 ram_nsec(fuc, 1000);
286
287 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
288 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
289 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
290 ram_wr32(fuc, 0x10f090, 0x00000061);
291 ram_wr32(fuc, 0x10f090, 0xc000007f);
292 ram_nsec(fuc, 1000);
293
294 ram_wr32(fuc, 0x10f698, 0x00000000);
295 ram_wr32(fuc, 0x10f69c, 0x00000000);
296
297 /*XXX: there does appear to be some kind of condition here, simply
298 * modifying these bits in the vbios from the default pl0
299 * entries shows no change. however, the data does appear to
300 * be correct and may be required for the transition back
301 */
302 mask = 0x800f07e0;
303 data = 0x00030000;
304 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
305 data |= 0x00040000;
306
307 if (1) {
308 data |= 0x800807e0;
309 switch (next->bios.ramcfg_11_03_c0) {
310 case 3: data &= ~0x00000040; break;
311 case 2: data &= ~0x00000100; break;
312 case 1: data &= ~0x80000000; break;
313 case 0: data &= ~0x00000400; break;
314 }
315
316 switch (next->bios.ramcfg_11_03_30) {
317 case 3: data &= ~0x00000020; break;
318 case 2: data &= ~0x00000080; break;
319 case 1: data &= ~0x00080000; break;
320 case 0: data &= ~0x00000200; break;
321 }
322 }
323
324 if (next->bios.ramcfg_11_02_80)
325 mask |= 0x03000000;
326 if (next->bios.ramcfg_11_02_40)
327 mask |= 0x00002000;
328 if (next->bios.ramcfg_11_07_10)
329 mask |= 0x00004000;
330 if (next->bios.ramcfg_11_07_08)
331 mask |= 0x00000003;
332 else {
333 mask |= 0x34000000;
334 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
335 mask |= 0x40000000;
336 }
337 ram_mask(fuc, 0x10f824, mask, data);
338
339 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
340
341 if (ram->from == 2 && ram->mode != 2) {
342 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
343 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
344 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
345 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
346 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
347 r1373f4_init(fuc);
348 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
349 r1373f4_fini(fuc);
350 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
351 } else
352 if (ram->from != 2 && ram->mode != 2) {
353 r1373f4_init(fuc);
354 r1373f4_fini(fuc);
355 }
356
357 if (ram_have(fuc, gpioMV)) {
358 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
359 if (temp != ram_rd32(fuc, gpioMV)) {
360 ram_wr32(fuc, gpiotrig, 1);
361 ram_nsec(fuc, 64000);
362 }
363 }
364
365 if (next->bios.ramcfg_11_02_40 ||
366 next->bios.ramcfg_11_07_10) {
367 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
368 ram_nsec(fuc, 20000);
369 }
370
371 if (ram->from != 2 && ram->mode == 2) {
372 if (0 /*XXX: Titan */)
373 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
374 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
375 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
376 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
377 r1373f4_init(fuc);
378 r1373f4_fini(fuc);
379 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
380 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
381 } else
382 if (ram->from == 2 && ram->mode == 2) {
383 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
384 r1373f4_init(fuc);
385 r1373f4_fini(fuc);
386 }
387
388 if (ram->mode != 2) /*XXX*/ {
389 if (next->bios.ramcfg_11_07_40)
390 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
391 }
392
393 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
394 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
395 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
396
397 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
398 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
399 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
400 } else
401 if (!next->bios.ramcfg_11_07_08) {
402 ram_wr32(fuc, 0x10f698, 0x00000000);
403 ram_wr32(fuc, 0x10f69c, 0x00000000);
404 }
405
406 if (ram->mode != 2) {
407 u32 data = 0x01000100 * next->bios.ramcfg_11_04;
408 ram_nuke(fuc, 0x10f694);
409 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
410 }
411
412 if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
413 data = 0x00000080;
414 else
415 data = 0x00000000;
416 ram_mask(fuc, 0x10f60c, 0x00000080, data);
417
418 mask = 0x00070000;
419 data = 0x00000000;
420 if (!next->bios.ramcfg_11_02_80)
421 data |= 0x03000000;
422 if (!next->bios.ramcfg_11_02_40)
423 data |= 0x00002000;
424 if (!next->bios.ramcfg_11_07_10)
425 data |= 0x00004000;
426 if (!next->bios.ramcfg_11_07_08)
427 data |= 0x00000003;
428 else
429 data |= 0x74000000;
430 ram_mask(fuc, 0x10f824, mask, data);
431
432 if (next->bios.ramcfg_11_01_08)
433 data = 0x00000000;
434 else
435 data = 0x00001000;
436 ram_mask(fuc, 0x10f200, 0x00001000, data);
437
438 if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
439 ram_nsec(fuc, 10000);
440 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
441 }
442
443 if (next->bios.ramcfg_11_08_01)
444 data = 0x00100000;
445 else
446 data = 0x00000000;
447 ram_mask(fuc, 0x10f82c, 0x00100000, data);
448
449 data = 0x00000000;
450 if (next->bios.ramcfg_11_08_08)
451 data |= 0x00002000;
452 if (next->bios.ramcfg_11_08_04)
453 data |= 0x00001000;
454 if (next->bios.ramcfg_11_08_02)
455 data |= 0x00004000;
456 ram_mask(fuc, 0x10f830, 0x00007000, data);
457
458 /* PFB timing */
459 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
460 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
461 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
462 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
463 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
464 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
465 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
466 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
467 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
468 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
469 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
470
471 data = mask = 0x00000000;
472 if (ram->diff.ramcfg_11_08_20) {
473 if (next->bios.ramcfg_11_08_20)
474 data |= 0x01000000;
475 mask |= 0x01000000;
476 }
477 ram_mask(fuc, 0x10f200, mask, data);
478
479 data = mask = 0x00000000;
480 if (ram->diff.ramcfg_11_02_03) {
481 data |= next->bios.ramcfg_11_02_03 << 8;
482 mask |= 0x00000300;
483 }
484 if (ram->diff.ramcfg_11_01_10) {
485 if (next->bios.ramcfg_11_01_10)
486 data |= 0x70000000;
487 mask |= 0x70000000;
488 }
489 ram_mask(fuc, 0x10f604, mask, data);
490
491 data = mask = 0x00000000;
492 if (ram->diff.timing_20_30_07) {
493 data |= next->bios.timing_20_30_07 << 28;
494 mask |= 0x70000000;
495 }
496 if (ram->diff.ramcfg_11_01_01) {
497 if (next->bios.ramcfg_11_01_01)
498 data |= 0x00000100;
499 mask |= 0x00000100;
500 }
501 ram_mask(fuc, 0x10f614, mask, data);
502
503 data = mask = 0x00000000;
504 if (ram->diff.timing_20_30_07) {
505 data |= next->bios.timing_20_30_07 << 28;
506 mask |= 0x70000000;
507 }
508 if (ram->diff.ramcfg_11_01_02) {
509 if (next->bios.ramcfg_11_01_02)
510 data |= 0x00000100;
511 mask |= 0x00000100;
512 }
513 ram_mask(fuc, 0x10f610, mask, data);
514
515 mask = 0x33f00000;
516 data = 0x00000000;
517 if (!next->bios.ramcfg_11_01_04)
518 data |= 0x20200000;
519 if (!next->bios.ramcfg_11_07_80)
520 data |= 0x12800000;
521 /*XXX: see note above about there probably being some condition
522 * for the 10f824 stuff that uses ramcfg 3...
523 */
524 if (next->bios.ramcfg_11_03_f0) {
525 if (next->bios.rammap_11_08_0c) {
526 if (!next->bios.ramcfg_11_07_80)
527 mask |= 0x00000020;
528 else
529 data |= 0x00000020;
530 mask |= 0x00000004;
531 }
532 } else {
533 mask |= 0x40000020;
534 data |= 0x00000004;
535 }
536
537 ram_mask(fuc, 0x10f808, mask, data);
538
539 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
540
541 data = mask = 0x00000000;
542 if (ram->diff.ramcfg_11_02_03) {
543 data |= next->bios.ramcfg_11_02_03;
544 mask |= 0x00000003;
545 }
546 if (ram->diff.ramcfg_11_01_10) {
547 if (next->bios.ramcfg_11_01_10)
548 data |= 0x00000004;
549 mask |= 0x00000004;
550 }
551
552 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
553 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
554 ram_wr32(fuc, 0x100710, 0x00000000);
555 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
556 }
557
558 data = next->bios.timing_20_30_07 << 8;
559 if (next->bios.ramcfg_11_01_01)
560 data |= 0x80000000;
561 ram_mask(fuc, 0x100778, 0x00000700, data);
562
563 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
564 data = (next->bios.timing[10] & 0x7f000000) >> 24;
565 if (data < next->bios.timing_20_2c_1fc0)
566 data = next->bios.timing_20_2c_1fc0;
567 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
568 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
569
570 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
571 next->bios.timing_20_31_0780 << 17 |
572 next->bios.timing_20_31_0078 << 8 |
573 next->bios.timing_20_31_0007);
574 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
575 next->bios.timing_20_31_7000);
576
577 ram_wr32(fuc, 0x10f090, 0x4000007e);
578 ram_nsec(fuc, 2000);
579 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
580 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
581 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
582
583 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
584 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
585 gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
586 ram_nsec(fuc, 1000);
587 ram_wr32(fuc, 0x10f294, temp);
588 }
589
590 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
591 ram_wr32(fuc, mr[0], ram->base.mr[0]);
592 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
593 ram_nsec(fuc, 1000);
594 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
595 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
596 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
597 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
598
599 if (vc == 0 && ram_have(fuc, gpio2E)) {
600 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
601 if (temp != ram_rd32(fuc, gpio2E)) {
602 ram_wr32(fuc, gpiotrig, 1);
603 ram_nsec(fuc, 20000);
604 }
605 }
606
607 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
608 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
609 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
610 ram_nsec(fuc, 1000);
611 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
612
613 data = ram_rd32(fuc, 0x10f978);
614 data &= ~0x00046144;
615 data |= 0x0000000b;
616 if (!next->bios.ramcfg_11_07_08) {
617 if (!next->bios.ramcfg_11_07_04)
618 data |= 0x0000200c;
619 else
620 data |= 0x00000000;
621 } else {
622 data |= 0x00040044;
623 }
624 ram_wr32(fuc, 0x10f978, data);
625
626 if (ram->mode == 1) {
627 data = ram_rd32(fuc, 0x10f830) | 0x00000001;
628 ram_wr32(fuc, 0x10f830, data);
629 }
630
631 if (!next->bios.ramcfg_11_07_08) {
632 data = 0x88020000;
633 if ( next->bios.ramcfg_11_07_04)
634 data |= 0x10000000;
635 if (!next->bios.rammap_11_08_10)
636 data |= 0x00080000;
637 } else {
638 data = 0xa40e0000;
639 }
640 gk104_ram_train(fuc, 0xbc0f0000, data);
641 if (1) /* XXX: not always? */
642 ram_nsec(fuc, 1000);
643
644 if (ram->mode == 2) { /*XXX*/
645 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
646 }
647
648 /* LP3 */
649 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
650 ram_nsec(fuc, 1000);
651
652 if (ram->mode != 2) {
653 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
654 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
655 }
656
657 if (next->bios.ramcfg_11_07_02)
658 gk104_ram_train(fuc, 0x80020000, 0x01000000);
659
660 ram_unblock(fuc);
661 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
662
663 if (next->bios.rammap_11_08_01)
664 data = 0x00000800;
665 else
666 data = 0x00000000;
667 ram_mask(fuc, 0x10f200, 0x00000800, data);
668 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
669 return 0;
670 }
671
672 /*******************************************************************************
673 * DDR3
674 ******************************************************************************/
675
676 static int
677 gk104_ram_calc_sddr3(struct nvkm_fb *pfb, u32 freq)
678 {
679 struct gk104_ram *ram = (void *)pfb->ram;
680 struct gk104_ramfuc *fuc = &ram->fuc;
681 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
682 const u32 runk0 = ram->fN1 << 16;
683 const u32 runk1 = ram->fN1;
684 struct nvkm_ram_data *next = ram->base.next;
685 int vc = !next->bios.ramcfg_11_02_08;
686 int mv = !next->bios.ramcfg_11_02_04;
687 u32 mask, data;
688
689 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
690 ram_block(fuc);
691 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
692
693 if (vc == 1 && ram_have(fuc, gpio2E)) {
694 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
695 if (temp != ram_rd32(fuc, gpio2E)) {
696 ram_wr32(fuc, gpiotrig, 1);
697 ram_nsec(fuc, 20000);
698 }
699 }
700
701 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
702 if (next->bios.ramcfg_11_03_f0)
703 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
704
705 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
706 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
707 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
708 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
709 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
710 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
711 ram_nsec(fuc, 1000);
712
713 ram_wr32(fuc, 0x10f090, 0x00000060);
714 ram_wr32(fuc, 0x10f090, 0xc000007e);
715
716 /*XXX: there does appear to be some kind of condition here, simply
717 * modifying these bits in the vbios from the default pl0
718 * entries shows no change. however, the data does appear to
719 * be correct and may be required for the transition back
720 */
721 mask = 0x00010000;
722 data = 0x00010000;
723
724 if (1) {
725 mask |= 0x800807e0;
726 data |= 0x800807e0;
727 switch (next->bios.ramcfg_11_03_c0) {
728 case 3: data &= ~0x00000040; break;
729 case 2: data &= ~0x00000100; break;
730 case 1: data &= ~0x80000000; break;
731 case 0: data &= ~0x00000400; break;
732 }
733
734 switch (next->bios.ramcfg_11_03_30) {
735 case 3: data &= ~0x00000020; break;
736 case 2: data &= ~0x00000080; break;
737 case 1: data &= ~0x00080000; break;
738 case 0: data &= ~0x00000200; break;
739 }
740 }
741
742 if (next->bios.ramcfg_11_02_80)
743 mask |= 0x03000000;
744 if (next->bios.ramcfg_11_02_40)
745 mask |= 0x00002000;
746 if (next->bios.ramcfg_11_07_10)
747 mask |= 0x00004000;
748 if (next->bios.ramcfg_11_07_08)
749 mask |= 0x00000003;
750 else
751 mask |= 0x14000000;
752 ram_mask(fuc, 0x10f824, mask, data);
753
754 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
755
756 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
757 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
758 data |= next->bios.ramcfg_11_03_30 << 16;
759 ram_wr32(fuc, 0x1373ec, data);
760 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
761 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
762
763 /* (re)program refpll, if required */
764 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
765 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
766 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
767 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
768 ram_wr32(fuc, 0x137320, 0x00000000);
769 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
770 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
771 ram_wr32(fuc, 0x132024, rcoef);
772 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
773 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
774 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
775 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
776 }
777
778 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
779 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
780 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
781
782 if (ram_have(fuc, gpioMV)) {
783 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
784 if (temp != ram_rd32(fuc, gpioMV)) {
785 ram_wr32(fuc, gpiotrig, 1);
786 ram_nsec(fuc, 64000);
787 }
788 }
789
790 if (next->bios.ramcfg_11_02_40 ||
791 next->bios.ramcfg_11_07_10) {
792 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
793 ram_nsec(fuc, 20000);
794 }
795
796 if (ram->mode != 2) /*XXX*/ {
797 if (next->bios.ramcfg_11_07_40)
798 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
799 }
800
801 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
802 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
803 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
804
805 mask = 0x00010000;
806 data = 0x00000000;
807 if (!next->bios.ramcfg_11_02_80)
808 data |= 0x03000000;
809 if (!next->bios.ramcfg_11_02_40)
810 data |= 0x00002000;
811 if (!next->bios.ramcfg_11_07_10)
812 data |= 0x00004000;
813 if (!next->bios.ramcfg_11_07_08)
814 data |= 0x00000003;
815 else
816 data |= 0x14000000;
817 ram_mask(fuc, 0x10f824, mask, data);
818 ram_nsec(fuc, 1000);
819
820 if (next->bios.ramcfg_11_08_01)
821 data = 0x00100000;
822 else
823 data = 0x00000000;
824 ram_mask(fuc, 0x10f82c, 0x00100000, data);
825
826 /* PFB timing */
827 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
828 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
829 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
830 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
831 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
832 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
833 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
834 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
835 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
836 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
837 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
838
839 mask = 0x33f00000;
840 data = 0x00000000;
841 if (!next->bios.ramcfg_11_01_04)
842 data |= 0x20200000;
843 if (!next->bios.ramcfg_11_07_80)
844 data |= 0x12800000;
845 /*XXX: see note above about there probably being some condition
846 * for the 10f824 stuff that uses ramcfg 3...
847 */
848 if (next->bios.ramcfg_11_03_f0) {
849 if (next->bios.rammap_11_08_0c) {
850 if (!next->bios.ramcfg_11_07_80)
851 mask |= 0x00000020;
852 else
853 data |= 0x00000020;
854 mask |= 0x08000004;
855 }
856 data |= 0x04000000;
857 } else {
858 mask |= 0x44000020;
859 data |= 0x08000004;
860 }
861
862 ram_mask(fuc, 0x10f808, mask, data);
863
864 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
865
866 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
867
868 data = (next->bios.timing[10] & 0x7f000000) >> 24;
869 if (data < next->bios.timing_20_2c_1fc0)
870 data = next->bios.timing_20_2c_1fc0;
871 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
872
873 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
874
875 ram_wr32(fuc, 0x10f090, 0x4000007f);
876 ram_nsec(fuc, 1000);
877
878 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
879 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
880 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
881 ram_nsec(fuc, 1000);
882
883 ram_nuke(fuc, mr[0]);
884 ram_mask(fuc, mr[0], 0x100, 0x100);
885 ram_mask(fuc, mr[0], 0x100, 0x000);
886
887 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
888 ram_wr32(fuc, mr[0], ram->base.mr[0]);
889 ram_nsec(fuc, 1000);
890
891 ram_nuke(fuc, mr[0]);
892 ram_mask(fuc, mr[0], 0x100, 0x100);
893 ram_mask(fuc, mr[0], 0x100, 0x000);
894
895 if (vc == 0 && ram_have(fuc, gpio2E)) {
896 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
897 if (temp != ram_rd32(fuc, gpio2E)) {
898 ram_wr32(fuc, gpiotrig, 1);
899 ram_nsec(fuc, 20000);
900 }
901 }
902
903 if (ram->mode != 2) {
904 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
905 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
906 }
907
908 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
909 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
910 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
911 ram_nsec(fuc, 1000);
912
913 ram_unblock(fuc);
914 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
915
916 if (next->bios.rammap_11_08_01)
917 data = 0x00000800;
918 else
919 data = 0x00000000;
920 ram_mask(fuc, 0x10f200, 0x00000800, data);
921 return 0;
922 }
923
924 /*******************************************************************************
925 * main hooks
926 ******************************************************************************/
927
928 static int
929 gk104_ram_calc_data(struct nvkm_fb *pfb, u32 khz, struct nvkm_ram_data *data)
930 {
931 struct gk104_ram *ram = (void *)pfb->ram;
932 struct nvkm_ram_data *cfg;
933 u32 mhz = khz / 1000;
934
935 list_for_each_entry(cfg, &ram->cfg, head) {
936 if (mhz >= cfg->bios.rammap_min &&
937 mhz <= cfg->bios.rammap_max) {
938 *data = *cfg;
939 data->freq = khz;
940 return 0;
941 }
942 }
943
944 nv_error(ram, "ramcfg data for %dMHz not found\n", mhz);
945 return -EINVAL;
946 }
947
948 static int
949 gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next)
950 {
951 struct gk104_ram *ram = (void *)pfb->ram;
952 struct gk104_ramfuc *fuc = &ram->fuc;
953 int refclk, i;
954 int ret;
955
956 ret = ram_init(fuc, pfb);
957 if (ret)
958 return ret;
959
960 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
961 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
962
963 /* XXX: this is *not* what nvidia do. on fermi nvidia generally
964 * select, based on some unknown condition, one of the two possible
965 * reference frequencies listed in the vbios table for mempll and
966 * program refpll to that frequency.
967 *
968 * so far, i've seen very weird values being chosen by nvidia on
969 * kepler boards, no idea how/why they're chosen.
970 */
971 refclk = next->freq;
972 if (ram->mode == 2)
973 refclk = fuc->mempll.refclk;
974
975 /* calculate refpll coefficients */
976 ret = gt215_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
977 &ram->fN1, &ram->M1, &ram->P1);
978 fuc->mempll.refclk = ret;
979 if (ret <= 0) {
980 nv_error(pfb, "unable to calc refpll\n");
981 return -EINVAL;
982 }
983
984 /* calculate mempll coefficients, if we're using it */
985 if (ram->mode == 2) {
986 /* post-divider doesn't work... the reg takes the values but
987 * appears to completely ignore it. there *is* a bit at
988 * bit 28 that appears to divide the clock by 2 if set.
989 */
990 fuc->mempll.min_p = 1;
991 fuc->mempll.max_p = 2;
992
993 ret = gt215_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
994 &ram->N2, NULL, &ram->M2, &ram->P2);
995 if (ret <= 0) {
996 nv_error(pfb, "unable to calc mempll\n");
997 return -EINVAL;
998 }
999 }
1000
1001 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1002 if (ram_have(fuc, mr[i]))
1003 ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1004 }
1005 ram->base.freq = next->freq;
1006
1007 switch (ram->base.type) {
1008 case NV_MEM_TYPE_DDR3:
1009 ret = nvkm_sddr3_calc(&ram->base);
1010 if (ret == 0)
1011 ret = gk104_ram_calc_sddr3(pfb, next->freq);
1012 break;
1013 case NV_MEM_TYPE_GDDR5:
1014 ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0);
1015 if (ret == 0)
1016 ret = gk104_ram_calc_gddr5(pfb, next->freq);
1017 break;
1018 default:
1019 ret = -ENOSYS;
1020 break;
1021 }
1022
1023 return ret;
1024 }
1025
1026 static int
1027 gk104_ram_calc(struct nvkm_fb *pfb, u32 freq)
1028 {
1029 struct nvkm_clk *clk = nvkm_clk(pfb);
1030 struct gk104_ram *ram = (void *)pfb->ram;
1031 struct nvkm_ram_data *xits = &ram->base.xition;
1032 struct nvkm_ram_data *copy;
1033 int ret;
1034
1035 if (ram->base.next == NULL) {
1036 ret = gk104_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem),
1037 &ram->base.former);
1038 if (ret)
1039 return ret;
1040
1041 ret = gk104_ram_calc_data(pfb, freq, &ram->base.target);
1042 if (ret)
1043 return ret;
1044
1045 if (ram->base.target.freq < ram->base.former.freq) {
1046 *xits = ram->base.target;
1047 copy = &ram->base.former;
1048 } else {
1049 *xits = ram->base.former;
1050 copy = &ram->base.target;
1051 }
1052
1053 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
1054 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
1055 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
1056
1057 ram->base.next = &ram->base.target;
1058 if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
1059 ram->base.next = &ram->base.xition;
1060 } else {
1061 BUG_ON(ram->base.next != &ram->base.xition);
1062 ram->base.next = &ram->base.target;
1063 }
1064
1065 return gk104_ram_calc_xits(pfb, ram->base.next);
1066 }
1067
1068 static void
1069 gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq)
1070 {
1071 struct gk104_ram *ram = (void *)pfb->ram;
1072 struct nvkm_ram_data *cfg;
1073 u32 mhz = freq / 1000;
1074 u32 mask, data;
1075
1076 list_for_each_entry(cfg, &ram->cfg, head) {
1077 if (mhz >= cfg->bios.rammap_min &&
1078 mhz <= cfg->bios.rammap_max)
1079 break;
1080 }
1081
1082 if (&cfg->head == &ram->cfg)
1083 return;
1084
1085 if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
1086 data |= cfg->bios.rammap_11_0a_03fe << 12;
1087 mask |= 0x001ff000;
1088 }
1089 if (ram->diff.rammap_11_09_01ff) {
1090 data |= cfg->bios.rammap_11_09_01ff;
1091 mask |= 0x000001ff;
1092 }
1093 nv_mask(pfb, 0x10f468, mask, data);
1094
1095 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
1096 data |= cfg->bios.rammap_11_0a_0400;
1097 mask |= 0x00000001;
1098 }
1099 nv_mask(pfb, 0x10f420, mask, data);
1100
1101 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
1102 data |= cfg->bios.rammap_11_0a_0800;
1103 mask |= 0x00000001;
1104 }
1105 nv_mask(pfb, 0x10f430, mask, data);
1106
1107 if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
1108 data |= cfg->bios.rammap_11_0b_01f0;
1109 mask |= 0x0000001f;
1110 }
1111 nv_mask(pfb, 0x10f400, mask, data);
1112
1113 if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
1114 data |= cfg->bios.rammap_11_0b_0200 << 9;
1115 mask |= 0x00000200;
1116 }
1117 nv_mask(pfb, 0x10f410, mask, data);
1118
1119 if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
1120 data |= cfg->bios.rammap_11_0d << 16;
1121 mask |= 0x00ff0000;
1122 }
1123 if (ram->diff.rammap_11_0f) {
1124 data |= cfg->bios.rammap_11_0f << 8;
1125 mask |= 0x0000ff00;
1126 }
1127 nv_mask(pfb, 0x10f440, mask, data);
1128
1129 if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
1130 data |= cfg->bios.rammap_11_0e << 8;
1131 mask |= 0x0000ff00;
1132 }
1133 if (ram->diff.rammap_11_0b_0800) {
1134 data |= cfg->bios.rammap_11_0b_0800 << 7;
1135 mask |= 0x00000080;
1136 }
1137 if (ram->diff.rammap_11_0b_0400) {
1138 data |= cfg->bios.rammap_11_0b_0400 << 5;
1139 mask |= 0x00000020;
1140 }
1141 nv_mask(pfb, 0x10f444, mask, data);
1142 }
1143
1144 static int
1145 gk104_ram_prog(struct nvkm_fb *pfb)
1146 {
1147 struct nvkm_device *device = nv_device(pfb);
1148 struct gk104_ram *ram = (void *)pfb->ram;
1149 struct gk104_ramfuc *fuc = &ram->fuc;
1150 struct nvkm_ram_data *next = ram->base.next;
1151
1152 if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) {
1153 ram_exec(fuc, false);
1154 return (ram->base.next == &ram->base.xition);
1155 }
1156
1157 gk104_ram_prog_0(pfb, 1000);
1158 ram_exec(fuc, true);
1159 gk104_ram_prog_0(pfb, next->freq);
1160
1161 return (ram->base.next == &ram->base.xition);
1162 }
1163
1164 static void
1165 gk104_ram_tidy(struct nvkm_fb *pfb)
1166 {
1167 struct gk104_ram *ram = (void *)pfb->ram;
1168 struct gk104_ramfuc *fuc = &ram->fuc;
1169 ram->base.next = NULL;
1170 ram_exec(fuc, false);
1171 }
1172
1173 struct gk104_ram_train {
1174 u16 mask;
1175 struct nvbios_M0209S remap;
1176 struct nvbios_M0209S type00;
1177 struct nvbios_M0209S type01;
1178 struct nvbios_M0209S type04;
1179 struct nvbios_M0209S type06;
1180 struct nvbios_M0209S type07;
1181 struct nvbios_M0209S type08;
1182 struct nvbios_M0209S type09;
1183 };
1184
1185 static int
1186 gk104_ram_train_type(struct nvkm_fb *pfb, int i, u8 ramcfg,
1187 struct gk104_ram_train *train)
1188 {
1189 struct nvkm_bios *bios = nvkm_bios(pfb);
1190 struct nvbios_M0205E M0205E;
1191 struct nvbios_M0205S M0205S;
1192 struct nvbios_M0209E M0209E;
1193 struct nvbios_M0209S *remap = &train->remap;
1194 struct nvbios_M0209S *value;
1195 u8 ver, hdr, cnt, len;
1196 u32 data;
1197
1198 /* determine type of data for this index */
1199 if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
1200 return -ENOENT;
1201
1202 switch (M0205E.type) {
1203 case 0x00: value = &train->type00; break;
1204 case 0x01: value = &train->type01; break;
1205 case 0x04: value = &train->type04; break;
1206 case 0x06: value = &train->type06; break;
1207 case 0x07: value = &train->type07; break;
1208 case 0x08: value = &train->type08; break;
1209 case 0x09: value = &train->type09; break;
1210 default:
1211 return 0;
1212 }
1213
1214 /* training data index determined by ramcfg strap */
1215 if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
1216 return -EINVAL;
1217 i = M0205S.data;
1218
1219 /* training data format information */
1220 if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
1221 return -EINVAL;
1222
1223 /* ... and the raw data */
1224 if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
1225 return -EINVAL;
1226
1227 if (M0209E.v02_07 == 2) {
1228 /* of course! why wouldn't we have a pointer to another entry
1229 * in the same table, and use the first one as an array of
1230 * remap indices...
1231 */
1232 if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
1233 remap)))
1234 return -EINVAL;
1235
1236 for (i = 0; i < ARRAY_SIZE(value->data); i++)
1237 value->data[i] = remap->data[value->data[i]];
1238 } else
1239 if (M0209E.v02_07 != 1)
1240 return -EINVAL;
1241
1242 train->mask |= 1 << M0205E.type;
1243 return 0;
1244 }
1245
1246 static int
1247 gk104_ram_train_init_0(struct nvkm_fb *pfb, struct gk104_ram_train *train)
1248 {
1249 int i, j;
1250
1251 if ((train->mask & 0x03d3) != 0x03d3) {
1252 nv_warn(pfb, "missing link training data\n");
1253 return -EINVAL;
1254 }
1255
1256 for (i = 0; i < 0x30; i++) {
1257 for (j = 0; j < 8; j += 4) {
1258 nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8));
1259 nv_wr32(pfb, 0x10f920 + j, 0x00000000 |
1260 train->type08.data[i] << 4 |
1261 train->type06.data[i]);
1262 nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]);
1263 nv_wr32(pfb, 0x10f920 + j, 0x00000100 |
1264 train->type09.data[i] << 4 |
1265 train->type07.data[i]);
1266 nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]);
1267 }
1268 }
1269
1270 for (j = 0; j < 8; j += 4) {
1271 for (i = 0; i < 0x100; i++) {
1272 nv_wr32(pfb, 0x10f968 + j, i);
1273 nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]);
1274 }
1275 }
1276
1277 return 0;
1278 }
1279
1280 static int
1281 gk104_ram_train_init(struct nvkm_fb *pfb)
1282 {
1283 u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
1284 struct gk104_ram_train *train;
1285 int ret = -ENOMEM, i;
1286
1287 if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) {
1288 for (i = 0; i < 0x100; i++) {
1289 ret = gk104_ram_train_type(pfb, i, ramcfg, train);
1290 if (ret && ret != -ENOENT)
1291 break;
1292 }
1293 }
1294
1295 switch (pfb->ram->type) {
1296 case NV_MEM_TYPE_GDDR5:
1297 ret = gk104_ram_train_init_0(pfb, train);
1298 break;
1299 default:
1300 ret = 0;
1301 break;
1302 }
1303
1304 kfree(train);
1305 return ret;
1306 }
1307
1308 int
1309 gk104_ram_init(struct nvkm_object *object)
1310 {
1311 struct nvkm_fb *pfb = (void *)object->parent;
1312 struct gk104_ram *ram = (void *)object;
1313 struct nvkm_bios *bios = nvkm_bios(pfb);
1314 u8 ver, hdr, cnt, len, snr, ssz;
1315 u32 data, save;
1316 int ret, i;
1317
1318 ret = nvkm_ram_init(&ram->base);
1319 if (ret)
1320 return ret;
1321
1322 /* run a bunch of tables from rammap table. there's actually
1323 * individual pointers for each rammap entry too, but, nvidia
1324 * seem to just run the last two entries' scripts early on in
1325 * their init, and never again.. we'll just run 'em all once
1326 * for now.
1327 *
1328 * i strongly suspect that each script is for a separate mode
1329 * (likely selected by 0x10f65c's lower bits?), and the
1330 * binary driver skips the one that's already been setup by
1331 * the init tables.
1332 */
1333 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1334 if (!data || hdr < 0x15)
1335 return -EINVAL;
1336
1337 cnt = nv_ro08(bios, data + 0x14); /* guess at count */
1338 data = nv_ro32(bios, data + 0x10); /* guess u32... */
1339 save = nv_rd32(pfb, 0x10f65c) & 0x000000f0;
1340 for (i = 0; i < cnt; i++, data += 4) {
1341 if (i != save >> 4) {
1342 nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4);
1343 nvbios_exec(&(struct nvbios_init) {
1344 .subdev = nv_subdev(pfb),
1345 .bios = bios,
1346 .offset = nv_ro32(bios, data),
1347 .execute = 1,
1348 });
1349 }
1350 }
1351 nv_mask(pfb, 0x10f65c, 0x000000f0, save);
1352 nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000);
1353 nv_wr32(pfb, 0x10ecc0, 0xffffffff);
1354 nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010);
1355
1356 return gk104_ram_train_init(pfb);
1357 }
1358
1359 static int
1360 gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i)
1361 {
1362 struct nvkm_fb *pfb = (void *)nv_object(ram)->parent;
1363 struct nvkm_bios *bios = nvkm_bios(pfb);
1364 struct nvkm_ram_data *cfg;
1365 struct nvbios_ramcfg *d = &ram->diff;
1366 struct nvbios_ramcfg *p, *n;
1367 u8 ver, hdr, cnt, len;
1368 u32 data;
1369 int ret;
1370
1371 if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL)))
1372 return -ENOMEM;
1373 p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios;
1374 n = &cfg->bios;
1375
1376 /* memory config data for a range of target frequencies */
1377 data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios);
1378 if (ret = -ENOENT, !data)
1379 goto done;
1380 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12)
1381 goto done;
1382
1383 /* ... and a portion specific to the attached memory */
1384 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg,
1385 &ver, &hdr, &cfg->bios);
1386 if (ret = -EINVAL, !data)
1387 goto done;
1388 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a)
1389 goto done;
1390
1391 /* lookup memory timings, if bios says they're present */
1392 if (cfg->bios.ramcfg_timing != 0xff) {
1393 data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing,
1394 &ver, &hdr, &cnt, &len,
1395 &cfg->bios);
1396 if (ret = -EINVAL, !data)
1397 goto done;
1398 if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33)
1399 goto done;
1400 }
1401
1402 list_add_tail(&cfg->head, &ram->cfg);
1403 if (ret = 0, i == 0)
1404 goto done;
1405
1406 d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe;
1407 d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff;
1408 d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400;
1409 d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800;
1410 d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0;
1411 d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200;
1412 d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d;
1413 d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f;
1414 d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e;
1415 d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800;
1416 d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400;
1417 d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01;
1418 d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02;
1419 d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10;
1420 d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03;
1421 d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20;
1422 d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07;
1423 done:
1424 if (ret)
1425 kfree(cfg);
1426 return ret;
1427 }
1428
1429 static void
1430 gk104_ram_dtor(struct nvkm_object *object)
1431 {
1432 struct gk104_ram *ram = (void *)object;
1433 struct nvkm_ram_data *cfg, *tmp;
1434
1435 list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
1436 kfree(cfg);
1437 }
1438
1439 nvkm_ram_destroy(&ram->base);
1440 }
1441
1442 static int
1443 gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
1444 struct nvkm_oclass *oclass, void *data, u32 size,
1445 struct nvkm_object **pobject)
1446 {
1447 struct nvkm_fb *pfb = nvkm_fb(parent);
1448 struct nvkm_bios *bios = nvkm_bios(pfb);
1449 struct nvkm_gpio *gpio = nvkm_gpio(pfb);
1450 struct dcb_gpio_func func;
1451 struct gk104_ram *ram;
1452 int ret, i;
1453 u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb));
1454 u32 tmp;
1455
1456 ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram);
1457 *pobject = nv_object(ram);
1458 if (ret)
1459 return ret;
1460
1461 INIT_LIST_HEAD(&ram->cfg);
1462
1463 switch (ram->base.type) {
1464 case NV_MEM_TYPE_DDR3:
1465 case NV_MEM_TYPE_GDDR5:
1466 ram->base.calc = gk104_ram_calc;
1467 ram->base.prog = gk104_ram_prog;
1468 ram->base.tidy = gk104_ram_tidy;
1469 break;
1470 default:
1471 nv_warn(pfb, "reclocking of this RAM type is unsupported\n");
1472 break;
1473 }
1474
1475 /* calculate a mask of differently configured memory partitions,
1476 * because, of course reclocking wasn't complicated enough
1477 * already without having to treat some of them differently to
1478 * the others....
1479 */
1480 ram->parts = nv_rd32(pfb, 0x022438);
1481 ram->pmask = nv_rd32(pfb, 0x022554);
1482 ram->pnuts = 0;
1483 for (i = 0, tmp = 0; i < ram->parts; i++) {
1484 if (!(ram->pmask & (1 << i))) {
1485 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000));
1486 if (tmp && tmp != cfg1) {
1487 ram->pnuts |= (1 << i);
1488 continue;
1489 }
1490 tmp = cfg1;
1491 }
1492 }
1493
1494 /* parse bios data for all rammap table entries up-front, and
1495 * build information on whether certain fields differ between
1496 * any of the entries.
1497 *
1498 * the binary driver appears to completely ignore some fields
1499 * when all entries contain the same value. at first, it was
1500 * hoped that these were mere optimisations and the bios init
1501 * tables had configured as per the values here, but there is
1502 * evidence now to suggest that this isn't the case and we do
1503 * need to treat this condition as a "don't touch" indicator.
1504 */
1505 for (i = 0; !ret; i++) {
1506 ret = gk104_ram_ctor_data(ram, ramcfg, i);
1507 if (ret && ret != -ENOENT) {
1508 nv_error(pfb, "failed to parse ramcfg data\n");
1509 return ret;
1510 }
1511 }
1512
1513 /* parse bios data for both pll's */
1514 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1515 if (ret) {
1516 nv_error(pfb, "mclk refpll data not found\n");
1517 return ret;
1518 }
1519
1520 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1521 if (ret) {
1522 nv_error(pfb, "mclk pll data not found\n");
1523 return ret;
1524 }
1525
1526 /* lookup memory voltage gpios */
1527 ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1528 if (ret == 0) {
1529 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
1530 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
1531 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
1532 }
1533
1534 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1535 if (ret == 0) {
1536 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
1537 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
1538 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
1539 }
1540
1541 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1542
1543 ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1544 ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1545 ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1546 ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1547 ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1548 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1549 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1550 ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1551
1552 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1553 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1554 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1555 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1556 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1557 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1558 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1559 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1560 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1561 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1562 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1563 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1564 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1565 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1566 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1567 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1568 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1569 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1570 ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1571 ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1572 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1573
1574 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1575 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1576 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1577 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1578 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1579 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1580 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1581 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1582 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1583 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1584 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1585
1586 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1587 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1588 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1589
1590 switch (ram->base.type) {
1591 case NV_MEM_TYPE_GDDR5:
1592 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1593 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1594 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1595 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1596 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1597 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1598 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1599 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1600 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1601 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1602 break;
1603 case NV_MEM_TYPE_DDR3:
1604 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1605 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1606 break;
1607 default:
1608 break;
1609 }
1610
1611 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1612 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1613 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1614 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1615 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1616 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1617 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1618 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1619 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1620 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1621 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1622 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1623 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1624 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1625 ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1626 ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1627 return 0;
1628 }
1629
1630 struct nvkm_oclass
1631 gk104_ram_oclass = {
1632 .handle = 0,
1633 .ofuncs = &(struct nvkm_ofuncs) {
1634 .ctor = gk104_ram_ctor,
1635 .dtor = gk104_ram_dtor,
1636 .init = gk104_ram_init,
1637 .fini = _nvkm_ram_fini,
1638 }
1639 };
Linux with added FPC-III support