drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c

   1 /*
   2  * Copyright 2014 Roy Spliet
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Roy Spliet <rspliet@eclipso.eu>
  23  *          Ben Skeggs
  24  */
  25 #include "priv.h"
  26
  27 struct ramxlat {
  28         int id;
  29         u8 enc;
  30 };
  31
  32 static inline int
  33 ramxlat(const struct ramxlat *xlat, int id)
  34 {
  35         while (xlat->id >= 0) {
  36                 if (xlat->id == id)
  37                         return xlat->enc;
  38                 xlat++;
  39         }
  40         return -EINVAL;
  41 }
  42
  43 static const struct ramxlat
  44 ramddr2_cl[] = {
  45         { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 },
  46         /* The following are available in some, but not all DDR2 docs */
  47         { 7, 7 },
  48         { -1 }
  49 };
  50
  51 static const struct ramxlat
  52 ramddr2_wr[] = {
  53         { 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 },
  54         /* The following are available in some, but not all DDR2 docs */
  55         { 7, 6 },
  56         { -1 }
  57 };
  58
  59 int
  60 nvkm_sddr2_calc(struct nvkm_ram *ram)
  61 {
  62         int CL, WR, DLL = 0, ODT = 0;
  63
  64         switch (ram->next->bios.timing_ver) {
  65         case 0x10:
  66                 CL  = ram->next->bios.timing_10_CL;
  67                 WR  = ram->next->bios.timing_10_WR;
  68                 DLL = !ram->next->bios.ramcfg_10_DLLoff;
  69                 ODT = ram->next->bios.timing_10_ODT & 3;
  70                 break;
  71         case 0x20:
  72                 CL  = (ram->next->bios.timing[1] & 0x0000001f);
  73                 WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
  74                 break;
  75         default:
  76                 return -ENOSYS;
  77         }
  78
  79         CL  = ramxlat(ramddr2_cl, CL);
  80         WR  = ramxlat(ramddr2_wr, WR);
  81         if (CL < 0 || WR < 0)
  82                 return -EINVAL;
  83
  84         ram->mr[0] &= ~0xf70;
  85         ram->mr[0] |= (WR & 0x07) << 9;
  86         ram->mr[0] |= (CL & 0x07) << 4;
  87
  88         ram->mr[1] &= ~0x045;
  89         ram->mr[1] |= (ODT & 0x1) << 2;
  90         ram->mr[1] |= (ODT & 0x2) << 5;
  91         ram->mr[1] |= !DLL;
  92         return 0;
  93 }