drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  *          Roy Spliet <rspliet@eclipso.eu>
  24  */
  25 #include "priv.h"
  26
  27 struct ramxlat {
  28         int id;
  29         u8 enc;
  30 };
  31
  32 static inline int
  33 ramxlat(const struct ramxlat *xlat, int id)
  34 {
  35         while (xlat->id >= 0) {
  36                 if (xlat->id == id)
  37                         return xlat->enc;
  38                 xlat++;
  39         }
  40         return -EINVAL;
  41 }
  42
  43 static const struct ramxlat
  44 ramddr3_cl[] = {
  45         { 5, 2 }, { 6, 4 }, { 7, 6 }, { 8, 8 }, { 9, 10 }, { 10, 12 },
  46         { 11, 14 },
  47         /* the below are mentioned in some, but not all, ddr3 docs */
  48         { 12, 1 }, { 13, 3 }, { 14, 5 },
  49         { -1 }
  50 };
  51
  52 static const struct ramxlat
  53 ramddr3_wr[] = {
  54         { 5, 1 }, { 6, 2 }, { 7, 3 }, { 8, 4 }, { 10, 5 }, { 12, 6 },
  55         /* the below are mentioned in some, but not all, ddr3 docs */
  56         { 14, 7 }, { 16, 0 },
  57         { -1 }
  58 };
  59
  60 static const struct ramxlat
  61 ramddr3_cwl[] = {
  62         { 5, 0 }, { 6, 1 }, { 7, 2 }, { 8, 3 },
  63         /* the below are mentioned in some, but not all, ddr3 docs */
  64         { 9, 4 },
  65         { -1 }
  66 };
  67
  68 int
  69 nvkm_sddr3_calc(struct nvkm_ram *ram)
  70 {
  71         int CWL, CL, WR, DLL = 0, ODT = 0;
  72
  73         switch (ram->next->bios.timing_ver) {
  74         case 0x10:
  75                 if (ram->next->bios.timing_hdr < 0x17) {
  76                         /* XXX: NV50: Get CWL from the timing register */
  77                         return -ENOSYS;
  78                 }
  79                 CWL = ram->next->bios.timing_10_CWL;
  80                 CL  = ram->next->bios.timing_10_CL;
  81                 WR  = ram->next->bios.timing_10_WR;
  82                 DLL = !ram->next->bios.ramcfg_10_DLLoff;
  83                 ODT = ram->next->bios.timing_10_ODT;
  84                 break;
  85         case 0x20:
  86                 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
  87                 CL  = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
  88                 WR  = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
  89                 /* XXX: Get these values from the VBIOS instead */
  90                 DLL = !(ram->mr[1] & 0x1);
  91                 ODT =   (ram->mr[1] & 0x004) >> 2 |
  92                         (ram->mr[1] & 0x040) >> 5 |
  93                         (ram->mr[1] & 0x200) >> 7;
  94                 break;
  95         default:
  96                 return -ENOSYS;
  97         }
  98
  99         CWL = ramxlat(ramddr3_cwl, CWL);
 100         CL  = ramxlat(ramddr3_cl, CL);
 101         WR  = ramxlat(ramddr3_wr, WR);
 102         if (CL < 0 || CWL < 0 || WR < 0)
 103                 return -EINVAL;
 104
 105         ram->mr[0] &= ~0xf74;
 106         ram->mr[0] |= (WR & 0x07) << 9;
 107         ram->mr[0] |= (CL & 0x0e) << 3;
 108         ram->mr[0] |= (CL & 0x01) << 2;
 109
 110         ram->mr[1] &= ~0x245;
 111         ram->mr[1] |= (ODT & 0x1) << 2;
 112         ram->mr[1] |= (ODT & 0x2) << 5;
 113         ram->mr[1] |= (ODT & 0x4) << 7;
 114         ram->mr[1] |= !DLL;
 115
 116         ram->mr[2] &= ~0x038;
 117         ram->mr[2] |= (CWL & 0x07) << 3;
 118         return 0;
 119 }