ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / subdev / gpio / gf110.c
blob2c3bb255d1f8d67f6cf51682c0862eb80fd19e61
1 /*
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs
24 #include "priv.h"
26 void
27 gf110_gpio_reset(struct nvkm_gpio *gpio, u8 match)
29 struct nvkm_bios *bios = nvkm_bios(gpio);
30 u8 ver, len;
31 u16 entry;
32 int ent = -1;
34 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
35 u32 data = nv_ro32(bios, entry);
36 u8 line = (data & 0x0000003f);
37 u8 defs = !!(data & 0x00000080);
38 u8 func = (data & 0x0000ff00) >> 8;
39 u8 unk0 = (data & 0x00ff0000) >> 16;
40 u8 unk1 = (data & 0x1f000000) >> 24;
42 if ( func == DCB_GPIO_UNUSED ||
43 (match != DCB_GPIO_UNUSED && match != func))
44 continue;
46 gpio->set(gpio, 0, func, line, defs);
48 nv_mask(gpio, 0x00d610 + (line * 4), 0xff, unk0);
49 if (unk1--)
50 nv_mask(gpio, 0x00d740 + (unk1 * 4), 0xff, line);
54 int
55 gf110_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
57 u32 data = ((dir ^ 1) << 13) | (out << 12);
58 nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data);
59 nv_mask(gpio, 0x00d604, 0x00000001, 0x00000001); /* update? */
60 return 0;
63 int
64 gf110_gpio_sense(struct nvkm_gpio *gpio, int line)
66 return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000);
69 struct nvkm_oclass *
70 gf110_gpio_oclass = &(struct nvkm_gpio_impl) {
71 .base.handle = NV_SUBDEV(GPIO, 0xd0),
72 .base.ofuncs = &(struct nvkm_ofuncs) {
73 .ctor = _nvkm_gpio_ctor,
74 .dtor = _nvkm_gpio_dtor,
75 .init = _nvkm_gpio_init,
76 .fini = _nvkm_gpio_fini,
78 .lines = 32,
79 .intr_stat = g94_gpio_intr_stat,
80 .intr_mask = g94_gpio_intr_mask,
81 .drive = gf110_gpio_drive,
82 .sense = gf110_gpio_sense,
83 .reset = gf110_gpio_reset,
84 }.base;