ARM: pmu: add support for interrupt-affinity property
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / subdev / i2c / nv04.c
blob4cdf1c4893534e8bd35e05e50e4dcef6d0e9721f
1 /*
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs
24 #include "priv.h"
26 #include <subdev/vga.h>
28 struct nv04_i2c_priv {
29 struct nvkm_i2c base;
32 struct nv04_i2c_port {
33 struct nvkm_i2c_port base;
34 u8 drive;
35 u8 sense;
38 static void
39 nv04_i2c_drive_scl(struct nvkm_i2c_port *base, int state)
41 struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
42 struct nv04_i2c_port *port = (void *)base;
43 u8 val = nv_rdvgac(priv, 0, port->drive);
44 if (state) val |= 0x20;
45 else val &= 0xdf;
46 nv_wrvgac(priv, 0, port->drive, val | 0x01);
49 static void
50 nv04_i2c_drive_sda(struct nvkm_i2c_port *base, int state)
52 struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
53 struct nv04_i2c_port *port = (void *)base;
54 u8 val = nv_rdvgac(priv, 0, port->drive);
55 if (state) val |= 0x10;
56 else val &= 0xef;
57 nv_wrvgac(priv, 0, port->drive, val | 0x01);
60 static int
61 nv04_i2c_sense_scl(struct nvkm_i2c_port *base)
63 struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
64 struct nv04_i2c_port *port = (void *)base;
65 return !!(nv_rdvgac(priv, 0, port->sense) & 0x04);
68 static int
69 nv04_i2c_sense_sda(struct nvkm_i2c_port *base)
71 struct nv04_i2c_priv *priv = (void *)nvkm_i2c(base);
72 struct nv04_i2c_port *port = (void *)base;
73 return !!(nv_rdvgac(priv, 0, port->sense) & 0x08);
76 static const struct nvkm_i2c_func
77 nv04_i2c_func = {
78 .drive_scl = nv04_i2c_drive_scl,
79 .drive_sda = nv04_i2c_drive_sda,
80 .sense_scl = nv04_i2c_sense_scl,
81 .sense_sda = nv04_i2c_sense_sda,
84 static int
85 nv04_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
86 struct nvkm_oclass *oclass, void *data, u32 index,
87 struct nvkm_object **pobject)
89 struct dcb_i2c_entry *info = data;
90 struct nv04_i2c_port *port;
91 int ret;
93 ret = nvkm_i2c_port_create(parent, engine, oclass, index,
94 &nvkm_i2c_bit_algo, &nv04_i2c_func, &port);
95 *pobject = nv_object(port);
96 if (ret)
97 return ret;
99 port->drive = info->drive;
100 port->sense = info->sense;
101 return 0;
104 static struct nvkm_oclass
105 nv04_i2c_sclass[] = {
106 { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV04_BIT),
107 .ofuncs = &(struct nvkm_ofuncs) {
108 .ctor = nv04_i2c_port_ctor,
109 .dtor = _nvkm_i2c_port_dtor,
110 .init = _nvkm_i2c_port_init,
111 .fini = _nvkm_i2c_port_fini,
117 struct nvkm_oclass *
118 nv04_i2c_oclass = &(struct nvkm_i2c_impl) {
119 .base.handle = NV_SUBDEV(I2C, 0x04),
120 .base.ofuncs = &(struct nvkm_ofuncs) {
121 .ctor = _nvkm_i2c_ctor,
122 .dtor = _nvkm_i2c_dtor,
123 .init = _nvkm_i2c_init,
124 .fini = _nvkm_i2c_fini,
126 .sclass = nv04_i2c_sclass,
127 .pad_x = &nv04_i2c_pad_oclass,
128 }.base;