drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv04.h"
  25
  26 int
  27 nv44_mc_init(struct nvkm_object *object)
  28 {
  29         struct nv04_mc_priv *priv = (void *)object;
  30         u32 tmp = nv_rd32(priv, 0x10020c);
  31
  32         nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */
  33
  34         nv_wr32(priv, 0x001700, tmp);
  35         nv_wr32(priv, 0x001704, 0);
  36         nv_wr32(priv, 0x001708, 0);
  37         nv_wr32(priv, 0x00170c, tmp);
  38
  39         return nvkm_mc_init(&priv->base);
  40 }
  41
  42 struct nvkm_oclass *
  43 nv44_mc_oclass = &(struct nvkm_mc_oclass) {
  44         .base.handle = NV_SUBDEV(MC, 0x44),
  45         .base.ofuncs = &(struct nvkm_ofuncs) {
  46                 .ctor = nv04_mc_ctor,
  47                 .dtor = _nvkm_mc_dtor,
  48                 .init = nv44_mc_init,
  49                 .fini = _nvkm_mc_fini,
  50         },
  51         .intr = nv04_mc_intr,
  52         .msi_rearm = nv40_mc_msi_rearm,
  53 }.base;