drivers/gpu/drm/rcar-du/rcar_du_group.c

   1 /*
   2  * rcar_du_group.c  --  R-Car Display Unit Channels Pair
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 /*
  15  * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
  16  * unit, timings generator, ...) and device-global resources (start/stop
  17  * control, planes, ...) shared between the two CRTCs.
  18  *
  19  * The R8A7790 introduced a third CRTC with its own set of global resources.
  20  * This would be modeled as two separate DU device instances if it wasn't for
  21  * a handful or resources that are shared between the three CRTCs (mostly
  22  * related to input and output routing). For this reason the R8A7790 DU must be
  23  * modeled as a single device with three CRTCs, two sets of "semi-global"
  24  * resources, and a few device-global resources.
  25  *
  26  * The rcar_du_group object is a driver specific object, without any real
  27  * counterpart in the DU documentation, that models those semi-global resources.
  28  */
  29
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32
  33 #include "rcar_du_drv.h"
  34 #include "rcar_du_group.h"
  35 #include "rcar_du_regs.h"
  36
  37 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
  38 {
  39         return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
  40 }
  41
  42 void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
  43 {
  44         rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
  45 }
  46
  47 static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
  48 {
  49         u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
  50
  51         /* The DEFR8 register for the first group also controls RGB output
  52          * routing to DPAD0
  53          */
  54         if (rgrp->index == 0)
  55                 defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
  56
  57         rcar_du_group_write(rgrp, DEFR8, defr8);
  58 }
  59
  60 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
  61 {
  62         /* Enable extended features */
  63         rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
  64         rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
  65         rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
  66         rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
  67         rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
  68
  69         if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
  70                 rcar_du_group_setup_defr8(rgrp);
  71
  72                 /* Configure input dot clock routing. We currently hardcode the
  73                  * configuration to routing DOTCLKINn to DUn.
  74                  */
  75                 rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE |
  76                                     DIDSR_LCDS_DCLKIN(2) |
  77                                     DIDSR_LCDS_DCLKIN(1) |
  78                                     DIDSR_LCDS_DCLKIN(0) |
  79                                     DIDSR_PDCS_CLK(2, 0) |
  80                                     DIDSR_PDCS_CLK(1, 0) |
  81                                     DIDSR_PDCS_CLK(0, 0));
  82         }
  83
  84         /* Use DS1PR and DS2PR to configure planes priorities and connects the
  85          * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
  86          */
  87         rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
  88 }
  89
  90 /*
  91  * rcar_du_group_get - Acquire a reference to the DU channels group
  92  *
  93  * Acquiring the first reference setups core registers. A reference must be held
  94  * before accessing any hardware registers.
  95  *
  96  * This function must be called with the DRM mode_config lock held.
  97  *
  98  * Return 0 in case of success or a negative error code otherwise.
  99  */
 100 int rcar_du_group_get(struct rcar_du_group *rgrp)
 101 {
 102         if (rgrp->use_count)
 103                 goto done;
 104
 105         rcar_du_group_setup(rgrp);
 106
 107 done:
 108         rgrp->use_count++;
 109         return 0;
 110 }
 111
 112 /*
 113  * rcar_du_group_put - Release a reference to the DU
 114  *
 115  * This function must be called with the DRM mode_config lock held.
 116  */
 117 void rcar_du_group_put(struct rcar_du_group *rgrp)
 118 {
 119         --rgrp->use_count;
 120 }
 121
 122 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 123 {
 124         rcar_du_group_write(rgrp, DSYSR,
 125                 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
 126                 (start ? DSYSR_DEN : DSYSR_DRES));
 127 }
 128
 129 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 130 {
 131         /* Many of the configuration bits are only updated when the display
 132          * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
 133          * of those bits could be pre-configured, but others (especially the
 134          * bits related to plane assignment to display timing controllers) need
 135          * to be modified at runtime.
 136          *
 137          * Restart the display controller if a start is requested. Sorry for the
 138          * flicker. It should be possible to move most of the "DRES-update" bits
 139          * setup to driver initialization time and minimize the number of cases
 140          * when the display controller will have to be restarted.
 141          */
 142         if (start) {
 143                 if (rgrp->used_crtcs++ != 0)
 144                         __rcar_du_group_start_stop(rgrp, false);
 145                 __rcar_du_group_start_stop(rgrp, true);
 146         } else {
 147                 if (--rgrp->used_crtcs == 0)
 148                         __rcar_du_group_start_stop(rgrp, false);
 149         }
 150 }
 151
 152 void rcar_du_group_restart(struct rcar_du_group *rgrp)
 153 {
 154         __rcar_du_group_start_stop(rgrp, false);
 155         __rcar_du_group_start_stop(rgrp, true);
 156 }
 157
 158 static int rcar_du_set_dpad0_routing(struct rcar_du_device *rcdu)
 159 {
 160         int ret;
 161
 162         if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
 163                 return 0;
 164
 165         /* RGB output routing to DPAD0 is configured in the DEFR8 register of
 166          * the first group. As this function can be called with the DU0 and DU1
 167          * CRTCs disabled, we need to enable the first group clock before
 168          * accessing the register.
 169          */
 170         ret = clk_prepare_enable(rcdu->crtcs[0].clock);
 171         if (ret < 0)
 172                 return ret;
 173
 174         rcar_du_group_setup_defr8(&rcdu->groups[0]);
 175
 176         clk_disable_unprepare(rcdu->crtcs[0].clock);
 177
 178         return 0;
 179 }
 180
 181 int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
 182 {
 183         struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
 184         u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 185
 186         dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
 187
 188         /* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
 189          * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
 190          * by default.
 191          */
 192         if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
 193                 dorcr |= DORCR_PG2D_DS1;
 194         else
 195                 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
 196
 197         rcar_du_group_write(rgrp, DORCR, dorcr);
 198
 199         return rcar_du_set_dpad0_routing(rgrp->dev);
 200 }