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Convert trailing spaces and periods in path components
[linux/fpc-iii.git] / drivers / bus / ti-sysc.c
blob770a780dfa5448792259cebf5a7092021ed8d802
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 */
5
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_domain.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/slab.h>
18 #include <linux/iopoll.h>
19
20 #include <linux/platform_data/ti-sysc.h>
21
22 #include <dt-bindings/bus/ti-sysc.h>
23
24 #define MAX_MODULE_SOFTRESET_WAIT 10000
25
26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
27
28 enum sysc_clocks {
29 SYSC_FCK,
30 SYSC_ICK,
31 SYSC_OPTFCK0,
32 SYSC_OPTFCK1,
33 SYSC_OPTFCK2,
34 SYSC_OPTFCK3,
35 SYSC_OPTFCK4,
36 SYSC_OPTFCK5,
37 SYSC_OPTFCK6,
38 SYSC_OPTFCK7,
39 SYSC_MAX_CLOCKS,
40 };
41
42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
45 };
46
47 #define SYSC_IDLEMODE_MASK 3
48 #define SYSC_CLOCKACTIVITY_MASK 3
49
50 /**
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
57 * @mdata: ti-sysc to hwmod translation data for a module
58 * @clocks: clocks used by the interconnect target module
59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
61 * @rsts: resets used by the interconnect target module
62 * @legacy_mode: configured for legacy mode if set
63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
65 * @cookie: data used by legacy platform callbacks
66 * @name: name if available
67 * @revision: interconnect target module revision
68 * @enabled: sysc runtime enabled status
69 * @needs_resume: runtime resume needed on resume from suspend
70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
73 * @pre_reset_quirk: module specific pre-reset quirk
74 * @post_reset_quirk: module specific post-reset quirk
75 * @reset_done_quirk: module specific reset done quirk
76 * @module_enable_quirk: module specific enable quirk
77 * @module_disable_quirk: module specific disable quirk
78 * @module_unlock_quirk: module specific sysconfig unlock quirk
79 * @module_lock_quirk: module specific sysconfig lock quirk
80 */
81 struct sysc {
82 struct device *dev;
83 u64 module_pa;
84 u32 module_size;
85 void __iomem *module_va;
86 int offsets[SYSC_MAX_REGS];
87 struct ti_sysc_module_data *mdata;
88 struct clk **clocks;
89 const char **clock_roles;
90 int nr_clocks;
91 struct reset_control *rsts;
92 const char *legacy_mode;
93 const struct sysc_capabilities *cap;
94 struct sysc_config cfg;
95 struct ti_sysc_cookie cookie;
96 const char *name;
97 u32 revision;
98 unsigned int enabled:1;
99 unsigned int needs_resume:1;
100 unsigned int child_needs_resume:1;
101 struct delayed_work idle_work;
102 void (*pre_reset_quirk)(struct sysc *sysc);
103 void (*post_reset_quirk)(struct sysc *sysc);
104 void (*reset_done_quirk)(struct sysc *sysc);
105 void (*module_enable_quirk)(struct sysc *sysc);
106 void (*module_disable_quirk)(struct sysc *sysc);
107 void (*module_unlock_quirk)(struct sysc *sysc);
108 void (*module_lock_quirk)(struct sysc *sysc);
109 };
110
111 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
112 bool is_child);
113
114 static void sysc_write(struct sysc *ddata, int offset, u32 value)
115 {
116 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
117 writew_relaxed(value & 0xffff, ddata->module_va + offset);
118
119 /* Only i2c revision has LO and HI register with stride of 4 */
120 if (ddata->offsets[SYSC_REVISION] >= 0 &&
121 offset == ddata->offsets[SYSC_REVISION]) {
122 u16 hi = value >> 16;
123
124 writew_relaxed(hi, ddata->module_va + offset + 4);
125 }
126
127 return;
128 }
129
130 writel_relaxed(value, ddata->module_va + offset);
131 }
132
133 static u32 sysc_read(struct sysc *ddata, int offset)
134 {
135 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
136 u32 val;
137
138 val = readw_relaxed(ddata->module_va + offset);
139
140 /* Only i2c revision has LO and HI register with stride of 4 */
141 if (ddata->offsets[SYSC_REVISION] >= 0 &&
142 offset == ddata->offsets[SYSC_REVISION]) {
143 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
144
145 val |= tmp << 16;
146 }
147
148 return val;
149 }
150
151 return readl_relaxed(ddata->module_va + offset);
152 }
153
154 static bool sysc_opt_clks_needed(struct sysc *ddata)
155 {
156 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
157 }
158
159 static u32 sysc_read_revision(struct sysc *ddata)
160 {
161 int offset = ddata->offsets[SYSC_REVISION];
162
163 if (offset < 0)
164 return 0;
165
166 return sysc_read(ddata, offset);
167 }
168
169 static u32 sysc_read_sysconfig(struct sysc *ddata)
170 {
171 int offset = ddata->offsets[SYSC_SYSCONFIG];
172
173 if (offset < 0)
174 return 0;
175
176 return sysc_read(ddata, offset);
177 }
178
179 static u32 sysc_read_sysstatus(struct sysc *ddata)
180 {
181 int offset = ddata->offsets[SYSC_SYSSTATUS];
182
183 if (offset < 0)
184 return 0;
185
186 return sysc_read(ddata, offset);
187 }
188
189 /* Poll on reset status */
190 static int sysc_wait_softreset(struct sysc *ddata)
191 {
192 u32 sysc_mask, syss_done, rstval;
193 int syss_offset, error = 0;
194
195 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
196 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
197
198 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
199 syss_done = 0;
200 else
201 syss_done = ddata->cfg.syss_mask;
202
203 if (syss_offset >= 0) {
204 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
205 rstval, (rstval & ddata->cfg.syss_mask) ==
206 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
207
208 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
209 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
210 rstval, !(rstval & sysc_mask),
211 100, MAX_MODULE_SOFTRESET_WAIT);
212 }
213
214 return error;
215 }
216
217 static int sysc_add_named_clock_from_child(struct sysc *ddata,
218 const char *name,
219 const char *optfck_name)
220 {
221 struct device_node *np = ddata->dev->of_node;
222 struct device_node *child;
223 struct clk_lookup *cl;
224 struct clk *clock;
225 const char *n;
226
227 if (name)
228 n = name;
229 else
230 n = optfck_name;
231
232 /* Does the clock alias already exist? */
233 clock = of_clk_get_by_name(np, n);
234 if (!IS_ERR(clock)) {
235 clk_put(clock);
236
237 return 0;
238 }
239
240 child = of_get_next_available_child(np, NULL);
241 if (!child)
242 return -ENODEV;
243
244 clock = devm_get_clk_from_child(ddata->dev, child, name);
245 if (IS_ERR(clock))
246 return PTR_ERR(clock);
247
248 /*
249 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
250 * limit for clk_get(). If cl ever needs to be freed, it should be done
251 * with clkdev_drop().
252 */
253 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
254 if (!cl)
255 return -ENOMEM;
256
257 cl->con_id = n;
258 cl->dev_id = dev_name(ddata->dev);
259 cl->clk = clock;
260 clkdev_add(cl);
261
262 clk_put(clock);
263
264 return 0;
265 }
266
267 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
268 {
269 const char *optfck_name;
270 int error, index;
271
272 if (ddata->nr_clocks < SYSC_OPTFCK0)
273 index = SYSC_OPTFCK0;
274 else
275 index = ddata->nr_clocks;
276
277 if (name)
278 optfck_name = name;
279 else
280 optfck_name = clock_names[index];
281
282 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
283 if (error)
284 return error;
285
286 ddata->clock_roles[index] = optfck_name;
287 ddata->nr_clocks++;
288
289 return 0;
290 }
291
292 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
293 {
294 int error, i, index = -ENODEV;
295
296 if (!strncmp(clock_names[SYSC_FCK], name, 3))
297 index = SYSC_FCK;
298 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
299 index = SYSC_ICK;
300
301 if (index < 0) {
302 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
303 if (!ddata->clocks[i]) {
304 index = i;
305 break;
306 }
307 }
308 }
309
310 if (index < 0) {
311 dev_err(ddata->dev, "clock %s not added\n", name);
312 return index;
313 }
314
315 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
316 if (IS_ERR(ddata->clocks[index])) {
317 dev_err(ddata->dev, "clock get error for %s: %li\n",
318 name, PTR_ERR(ddata->clocks[index]));
319
320 return PTR_ERR(ddata->clocks[index]);
321 }
322
323 error = clk_prepare(ddata->clocks[index]);
324 if (error) {
325 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
326 name, error);
327
328 return error;
329 }
330
331 return 0;
332 }
333
334 static int sysc_get_clocks(struct sysc *ddata)
335 {
336 struct device_node *np = ddata->dev->of_node;
337 struct property *prop;
338 const char *name;
339 int nr_fck = 0, nr_ick = 0, i, error = 0;
340
341 ddata->clock_roles = devm_kcalloc(ddata->dev,
342 SYSC_MAX_CLOCKS,
343 sizeof(*ddata->clock_roles),
344 GFP_KERNEL);
345 if (!ddata->clock_roles)
346 return -ENOMEM;
347
348 of_property_for_each_string(np, "clock-names", prop, name) {
349 if (!strncmp(clock_names[SYSC_FCK], name, 3))
350 nr_fck++;
351 if (!strncmp(clock_names[SYSC_ICK], name, 3))
352 nr_ick++;
353 ddata->clock_roles[ddata->nr_clocks] = name;
354 ddata->nr_clocks++;
355 }
356
357 if (ddata->nr_clocks < 1)
358 return 0;
359
360 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
361 error = sysc_init_ext_opt_clock(ddata, NULL);
362 if (error)
363 return error;
364 }
365
366 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
367 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
368
369 return -EINVAL;
370 }
371
372 if (nr_fck > 1 || nr_ick > 1) {
373 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
374
375 return -EINVAL;
376 }
377
378 /* Always add a slot for main clocks fck and ick even if unused */
379 if (!nr_fck)
380 ddata->nr_clocks++;
381 if (!nr_ick)
382 ddata->nr_clocks++;
383
384 ddata->clocks = devm_kcalloc(ddata->dev,
385 ddata->nr_clocks, sizeof(*ddata->clocks),
386 GFP_KERNEL);
387 if (!ddata->clocks)
388 return -ENOMEM;
389
390 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
391 const char *name = ddata->clock_roles[i];
392
393 if (!name)
394 continue;
395
396 error = sysc_get_one_clock(ddata, name);
397 if (error)
398 return error;
399 }
400
401 return 0;
402 }
403
404 static int sysc_enable_main_clocks(struct sysc *ddata)
405 {
406 struct clk *clock;
407 int i, error;
408
409 if (!ddata->clocks)
410 return 0;
411
412 for (i = 0; i < SYSC_OPTFCK0; i++) {
413 clock = ddata->clocks[i];
414
415 /* Main clocks may not have ick */
416 if (IS_ERR_OR_NULL(clock))
417 continue;
418
419 error = clk_enable(clock);
420 if (error)
421 goto err_disable;
422 }
423
424 return 0;
425
426 err_disable:
427 for (i--; i >= 0; i--) {
428 clock = ddata->clocks[i];
429
430 /* Main clocks may not have ick */
431 if (IS_ERR_OR_NULL(clock))
432 continue;
433
434 clk_disable(clock);
435 }
436
437 return error;
438 }
439
440 static void sysc_disable_main_clocks(struct sysc *ddata)
441 {
442 struct clk *clock;
443 int i;
444
445 if (!ddata->clocks)
446 return;
447
448 for (i = 0; i < SYSC_OPTFCK0; i++) {
449 clock = ddata->clocks[i];
450 if (IS_ERR_OR_NULL(clock))
451 continue;
452
453 clk_disable(clock);
454 }
455 }
456
457 static int sysc_enable_opt_clocks(struct sysc *ddata)
458 {
459 struct clk *clock;
460 int i, error;
461
462 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
463 return 0;
464
465 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
466 clock = ddata->clocks[i];
467
468 /* Assume no holes for opt clocks */
469 if (IS_ERR_OR_NULL(clock))
470 return 0;
471
472 error = clk_enable(clock);
473 if (error)
474 goto err_disable;
475 }
476
477 return 0;
478
479 err_disable:
480 for (i--; i >= 0; i--) {
481 clock = ddata->clocks[i];
482 if (IS_ERR_OR_NULL(clock))
483 continue;
484
485 clk_disable(clock);
486 }
487
488 return error;
489 }
490
491 static void sysc_disable_opt_clocks(struct sysc *ddata)
492 {
493 struct clk *clock;
494 int i;
495
496 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
497 return;
498
499 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
500 clock = ddata->clocks[i];
501
502 /* Assume no holes for opt clocks */
503 if (IS_ERR_OR_NULL(clock))
504 return;
505
506 clk_disable(clock);
507 }
508 }
509
510 static void sysc_clkdm_deny_idle(struct sysc *ddata)
511 {
512 struct ti_sysc_platform_data *pdata;
513
514 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
515 return;
516
517 pdata = dev_get_platdata(ddata->dev);
518 if (pdata && pdata->clkdm_deny_idle)
519 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
520 }
521
522 static void sysc_clkdm_allow_idle(struct sysc *ddata)
523 {
524 struct ti_sysc_platform_data *pdata;
525
526 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
527 return;
528
529 pdata = dev_get_platdata(ddata->dev);
530 if (pdata && pdata->clkdm_allow_idle)
531 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
532 }
533
534 /**
535 * sysc_init_resets - init rstctrl reset line if configured
536 * @ddata: device driver data
537 *
538 * See sysc_rstctrl_reset_deassert().
539 */
540 static int sysc_init_resets(struct sysc *ddata)
541 {
542 ddata->rsts =
543 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
544 if (IS_ERR(ddata->rsts))
545 return PTR_ERR(ddata->rsts);
546
547 return 0;
548 }
549
550 /**
551 * sysc_parse_and_check_child_range - parses module IO region from ranges
552 * @ddata: device driver data
553 *
554 * In general we only need rev, syss, and sysc registers and not the whole
555 * module range. But we do want the offsets for these registers from the
556 * module base. This allows us to check them against the legacy hwmod
557 * platform data. Let's also check the ranges are configured properly.
558 */
559 static int sysc_parse_and_check_child_range(struct sysc *ddata)
560 {
561 struct device_node *np = ddata->dev->of_node;
562 const __be32 *ranges;
563 u32 nr_addr, nr_size;
564 int len, error;
565
566 ranges = of_get_property(np, "ranges", &len);
567 if (!ranges) {
568 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
569
570 return -ENOENT;
571 }
572
573 len /= sizeof(*ranges);
574
575 if (len < 3) {
576 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
577
578 return -EINVAL;
579 }
580
581 error = of_property_read_u32(np, "#address-cells", &nr_addr);
582 if (error)
583 return -ENOENT;
584
585 error = of_property_read_u32(np, "#size-cells", &nr_size);
586 if (error)
587 return -ENOENT;
588
589 if (nr_addr != 1 || nr_size != 1) {
590 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
591
592 return -EINVAL;
593 }
594
595 ranges++;
596 ddata->module_pa = of_translate_address(np, ranges++);
597 ddata->module_size = be32_to_cpup(ranges);
598
599 return 0;
600 }
601
602 static struct device_node *stdout_path;
603
604 static void sysc_init_stdout_path(struct sysc *ddata)
605 {
606 struct device_node *np = NULL;
607 const char *uart;
608
609 if (IS_ERR(stdout_path))
610 return;
611
612 if (stdout_path)
613 return;
614
615 np = of_find_node_by_path("/chosen");
616 if (!np)
617 goto err;
618
619 uart = of_get_property(np, "stdout-path", NULL);
620 if (!uart)
621 goto err;
622
623 np = of_find_node_by_path(uart);
624 if (!np)
625 goto err;
626
627 stdout_path = np;
628
629 return;
630
631 err:
632 stdout_path = ERR_PTR(-ENODEV);
633 }
634
635 static void sysc_check_quirk_stdout(struct sysc *ddata,
636 struct device_node *np)
637 {
638 sysc_init_stdout_path(ddata);
639 if (np != stdout_path)
640 return;
641
642 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
643 SYSC_QUIRK_NO_RESET_ON_INIT;
644 }
645
646 /**
647 * sysc_check_one_child - check child configuration
648 * @ddata: device driver data
649 * @np: child device node
650 *
651 * Let's avoid messy situations where we have new interconnect target
652 * node but children have "ti,hwmods". These belong to the interconnect
653 * target node and are managed by this driver.
654 */
655 static void sysc_check_one_child(struct sysc *ddata,
656 struct device_node *np)
657 {
658 const char *name;
659
660 name = of_get_property(np, "ti,hwmods", NULL);
661 if (name)
662 dev_warn(ddata->dev, "really a child ti,hwmods property?");
663
664 sysc_check_quirk_stdout(ddata, np);
665 sysc_parse_dts_quirks(ddata, np, true);
666 }
667
668 static void sysc_check_children(struct sysc *ddata)
669 {
670 struct device_node *child;
671
672 for_each_child_of_node(ddata->dev->of_node, child)
673 sysc_check_one_child(ddata, child);
674 }
675
676 /*
677 * So far only I2C uses 16-bit read access with clockactivity with revision
678 * in two registers with stride of 4. We can detect this based on the rev
679 * register size to configure things far enough to be able to properly read
680 * the revision register.
681 */
682 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
683 {
684 if (resource_size(res) == 8)
685 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
686 }
687
688 /**
689 * sysc_parse_one - parses the interconnect target module registers
690 * @ddata: device driver data
691 * @reg: register to parse
692 */
693 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
694 {
695 struct resource *res;
696 const char *name;
697
698 switch (reg) {
699 case SYSC_REVISION:
700 case SYSC_SYSCONFIG:
701 case SYSC_SYSSTATUS:
702 name = reg_names[reg];
703 break;
704 default:
705 return -EINVAL;
706 }
707
708 res = platform_get_resource_byname(to_platform_device(ddata->dev),
709 IORESOURCE_MEM, name);
710 if (!res) {
711 ddata->offsets[reg] = -ENODEV;
712
713 return 0;
714 }
715
716 ddata->offsets[reg] = res->start - ddata->module_pa;
717 if (reg == SYSC_REVISION)
718 sysc_check_quirk_16bit(ddata, res);
719
720 return 0;
721 }
722
723 static int sysc_parse_registers(struct sysc *ddata)
724 {
725 int i, error;
726
727 for (i = 0; i < SYSC_MAX_REGS; i++) {
728 error = sysc_parse_one(ddata, i);
729 if (error)
730 return error;
731 }
732
733 return 0;
734 }
735
736 /**
737 * sysc_check_registers - check for misconfigured register overlaps
738 * @ddata: device driver data
739 */
740 static int sysc_check_registers(struct sysc *ddata)
741 {
742 int i, j, nr_regs = 0, nr_matches = 0;
743
744 for (i = 0; i < SYSC_MAX_REGS; i++) {
745 if (ddata->offsets[i] < 0)
746 continue;
747
748 if (ddata->offsets[i] > (ddata->module_size - 4)) {
749 dev_err(ddata->dev, "register outside module range");
750
751 return -EINVAL;
752 }
753
754 for (j = 0; j < SYSC_MAX_REGS; j++) {
755 if (ddata->offsets[j] < 0)
756 continue;
757
758 if (ddata->offsets[i] == ddata->offsets[j])
759 nr_matches++;
760 }
761 nr_regs++;
762 }
763
764 if (nr_matches > nr_regs) {
765 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
766 nr_regs, nr_matches);
767
768 return -EINVAL;
769 }
770
771 return 0;
772 }
773
774 /**
775 * syc_ioremap - ioremap register space for the interconnect target module
776 * @ddata: device driver data
777 *
778 * Note that the interconnect target module registers can be anywhere
779 * within the interconnect target module range. For example, SGX has
780 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
781 * has them at offset 0x1200 in the CPSW_WR child. Usually the
782 * the interconnect target module registers are at the beginning of
783 * the module range though.
784 */
785 static int sysc_ioremap(struct sysc *ddata)
786 {
787 int size;
788
789 if (ddata->offsets[SYSC_REVISION] < 0 &&
790 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
791 ddata->offsets[SYSC_SYSSTATUS] < 0) {
792 size = ddata->module_size;
793 } else {
794 size = max3(ddata->offsets[SYSC_REVISION],
795 ddata->offsets[SYSC_SYSCONFIG],
796 ddata->offsets[SYSC_SYSSTATUS]);
797
798 if (size < SZ_1K)
799 size = SZ_1K;
800
801 if ((size + sizeof(u32)) > ddata->module_size)
802 size = ddata->module_size;
803 }
804
805 ddata->module_va = devm_ioremap(ddata->dev,
806 ddata->module_pa,
807 size + sizeof(u32));
808 if (!ddata->module_va)
809 return -EIO;
810
811 return 0;
812 }
813
814 /**
815 * sysc_map_and_check_registers - ioremap and check device registers
816 * @ddata: device driver data
817 */
818 static int sysc_map_and_check_registers(struct sysc *ddata)
819 {
820 int error;
821
822 error = sysc_parse_and_check_child_range(ddata);
823 if (error)
824 return error;
825
826 sysc_check_children(ddata);
827
828 error = sysc_parse_registers(ddata);
829 if (error)
830 return error;
831
832 error = sysc_ioremap(ddata);
833 if (error)
834 return error;
835
836 error = sysc_check_registers(ddata);
837 if (error)
838 return error;
839
840 return 0;
841 }
842
843 /**
844 * sysc_show_rev - read and show interconnect target module revision
845 * @bufp: buffer to print the information to
846 * @ddata: device driver data
847 */
848 static int sysc_show_rev(char *bufp, struct sysc *ddata)
849 {
850 int len;
851
852 if (ddata->offsets[SYSC_REVISION] < 0)
853 return sprintf(bufp, ":NA");
854
855 len = sprintf(bufp, ":%08x", ddata->revision);
856
857 return len;
858 }
859
860 static int sysc_show_reg(struct sysc *ddata,
861 char *bufp, enum sysc_registers reg)
862 {
863 if (ddata->offsets[reg] < 0)
864 return sprintf(bufp, ":NA");
865
866 return sprintf(bufp, ":%x", ddata->offsets[reg]);
867 }
868
869 static int sysc_show_name(char *bufp, struct sysc *ddata)
870 {
871 if (!ddata->name)
872 return 0;
873
874 return sprintf(bufp, ":%s", ddata->name);
875 }
876
877 /**
878 * sysc_show_registers - show information about interconnect target module
879 * @ddata: device driver data
880 */
881 static void sysc_show_registers(struct sysc *ddata)
882 {
883 char buf[128];
884 char *bufp = buf;
885 int i;
886
887 for (i = 0; i < SYSC_MAX_REGS; i++)
888 bufp += sysc_show_reg(ddata, bufp, i);
889
890 bufp += sysc_show_rev(bufp, ddata);
891 bufp += sysc_show_name(bufp, ddata);
892
893 dev_dbg(ddata->dev, "%llx:%x%s\n",
894 ddata->module_pa, ddata->module_size,
895 buf);
896 }
897
898 /**
899 * sysc_write_sysconfig - handle sysconfig quirks for register write
900 * @ddata: device driver data
901 * @value: register value
902 */
903 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
904 {
905 if (ddata->module_unlock_quirk)
906 ddata->module_unlock_quirk(ddata);
907
908 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
909
910 if (ddata->module_lock_quirk)
911 ddata->module_lock_quirk(ddata);
912 }
913
914 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
915 #define SYSC_CLOCACT_ICK 2
916
917 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
918 static int sysc_enable_module(struct device *dev)
919 {
920 struct sysc *ddata;
921 const struct sysc_regbits *regbits;
922 u32 reg, idlemodes, best_mode;
923 int error;
924
925 ddata = dev_get_drvdata(dev);
926
927 /*
928 * Some modules like DSS reset automatically on idle. Enable optional
929 * reset clocks and wait for OCP softreset to complete.
930 */
931 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
932 error = sysc_enable_opt_clocks(ddata);
933 if (error) {
934 dev_err(ddata->dev,
935 "Optional clocks failed for enable: %i\n",
936 error);
937 return error;
938 }
939 }
940 error = sysc_wait_softreset(ddata);
941 if (error)
942 dev_warn(ddata->dev, "OCP softreset timed out\n");
943 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
944 sysc_disable_opt_clocks(ddata);
945
946 /*
947 * Some subsystem private interconnects, like DSS top level module,
948 * need only the automatic OCP softreset handling with no sysconfig
949 * register bits to configure.
950 */
951 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
952 return 0;
953
954 regbits = ddata->cap->regbits;
955 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
956
957 /*
958 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
959 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
960 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
961 */
962 if (regbits->clkact_shift >= 0 &&
963 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
964 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
965
966 /* Set SIDLE mode */
967 idlemodes = ddata->cfg.sidlemodes;
968 if (!idlemodes || regbits->sidle_shift < 0)
969 goto set_midle;
970
971 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
972 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
973 best_mode = SYSC_IDLE_NO;
974 } else {
975 best_mode = fls(ddata->cfg.sidlemodes) - 1;
976 if (best_mode > SYSC_IDLE_MASK) {
977 dev_err(dev, "%s: invalid sidlemode\n", __func__);
978 return -EINVAL;
979 }
980
981 /* Set WAKEUP */
982 if (regbits->enwkup_shift >= 0 &&
983 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
984 reg |= BIT(regbits->enwkup_shift);
985 }
986
987 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
988 reg |= best_mode << regbits->sidle_shift;
989 sysc_write_sysconfig(ddata, reg);
990
991 set_midle:
992 /* Set MIDLE mode */
993 idlemodes = ddata->cfg.midlemodes;
994 if (!idlemodes || regbits->midle_shift < 0)
995 goto set_autoidle;
996
997 best_mode = fls(ddata->cfg.midlemodes) - 1;
998 if (best_mode > SYSC_IDLE_MASK) {
999 dev_err(dev, "%s: invalid midlemode\n", __func__);
1000 return -EINVAL;
1001 }
1002
1003 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1004 best_mode = SYSC_IDLE_NO;
1005
1006 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1007 reg |= best_mode << regbits->midle_shift;
1008 sysc_write_sysconfig(ddata, reg);
1009
1010 set_autoidle:
1011 /* Autoidle bit must enabled separately if available */
1012 if (regbits->autoidle_shift >= 0 &&
1013 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1014 reg |= 1 << regbits->autoidle_shift;
1015 sysc_write_sysconfig(ddata, reg);
1016 }
1017
1018 /* Flush posted write */
1019 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1020
1021 if (ddata->module_enable_quirk)
1022 ddata->module_enable_quirk(ddata);
1023
1024 return 0;
1025 }
1026
1027 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1028 {
1029 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1030 *best_mode = SYSC_IDLE_SMART_WKUP;
1031 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1032 *best_mode = SYSC_IDLE_SMART;
1033 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1034 *best_mode = SYSC_IDLE_FORCE;
1035 else
1036 return -EINVAL;
1037
1038 return 0;
1039 }
1040
1041 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1042 static int sysc_disable_module(struct device *dev)
1043 {
1044 struct sysc *ddata;
1045 const struct sysc_regbits *regbits;
1046 u32 reg, idlemodes, best_mode;
1047 int ret;
1048
1049 ddata = dev_get_drvdata(dev);
1050 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1051 return 0;
1052
1053 if (ddata->module_disable_quirk)
1054 ddata->module_disable_quirk(ddata);
1055
1056 regbits = ddata->cap->regbits;
1057 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1058
1059 /* Set MIDLE mode */
1060 idlemodes = ddata->cfg.midlemodes;
1061 if (!idlemodes || regbits->midle_shift < 0)
1062 goto set_sidle;
1063
1064 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1065 if (ret) {
1066 dev_err(dev, "%s: invalid midlemode\n", __func__);
1067 return ret;
1068 }
1069
1070 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1071 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1072 best_mode = SYSC_IDLE_FORCE;
1073
1074 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1075 reg |= best_mode << regbits->midle_shift;
1076 sysc_write_sysconfig(ddata, reg);
1077
1078 set_sidle:
1079 /* Set SIDLE mode */
1080 idlemodes = ddata->cfg.sidlemodes;
1081 if (!idlemodes || regbits->sidle_shift < 0)
1082 return 0;
1083
1084 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1085 best_mode = SYSC_IDLE_FORCE;
1086 } else {
1087 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1088 if (ret) {
1089 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1090 return ret;
1091 }
1092 }
1093
1094 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1095 reg |= best_mode << regbits->sidle_shift;
1096 if (regbits->autoidle_shift >= 0 &&
1097 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1098 reg |= 1 << regbits->autoidle_shift;
1099 sysc_write_sysconfig(ddata, reg);
1100
1101 /* Flush posted write */
1102 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1103
1104 return 0;
1105 }
1106
1107 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1108 struct sysc *ddata)
1109 {
1110 struct ti_sysc_platform_data *pdata;
1111 int error;
1112
1113 pdata = dev_get_platdata(ddata->dev);
1114 if (!pdata)
1115 return 0;
1116
1117 if (!pdata->idle_module)
1118 return -ENODEV;
1119
1120 error = pdata->idle_module(dev, &ddata->cookie);
1121 if (error)
1122 dev_err(dev, "%s: could not idle: %i\n",
1123 __func__, error);
1124
1125 reset_control_assert(ddata->rsts);
1126
1127 return 0;
1128 }
1129
1130 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1131 struct sysc *ddata)
1132 {
1133 struct ti_sysc_platform_data *pdata;
1134 int error;
1135
1136 reset_control_deassert(ddata->rsts);
1137
1138 pdata = dev_get_platdata(ddata->dev);
1139 if (!pdata)
1140 return 0;
1141
1142 if (!pdata->enable_module)
1143 return -ENODEV;
1144
1145 error = pdata->enable_module(dev, &ddata->cookie);
1146 if (error)
1147 dev_err(dev, "%s: could not enable: %i\n",
1148 __func__, error);
1149
1150 return 0;
1151 }
1152
1153 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1154 {
1155 struct sysc *ddata;
1156 int error = 0;
1157
1158 ddata = dev_get_drvdata(dev);
1159
1160 if (!ddata->enabled)
1161 return 0;
1162
1163 sysc_clkdm_deny_idle(ddata);
1164
1165 if (ddata->legacy_mode) {
1166 error = sysc_runtime_suspend_legacy(dev, ddata);
1167 if (error)
1168 goto err_allow_idle;
1169 } else {
1170 error = sysc_disable_module(dev);
1171 if (error)
1172 goto err_allow_idle;
1173 }
1174
1175 sysc_disable_main_clocks(ddata);
1176
1177 if (sysc_opt_clks_needed(ddata))
1178 sysc_disable_opt_clocks(ddata);
1179
1180 ddata->enabled = false;
1181
1182 err_allow_idle:
1183 reset_control_assert(ddata->rsts);
1184
1185 sysc_clkdm_allow_idle(ddata);
1186
1187 return error;
1188 }
1189
1190 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1191 {
1192 struct sysc *ddata;
1193 int error = 0;
1194
1195 ddata = dev_get_drvdata(dev);
1196
1197 if (ddata->enabled)
1198 return 0;
1199
1200
1201 sysc_clkdm_deny_idle(ddata);
1202
1203 reset_control_deassert(ddata->rsts);
1204
1205 if (sysc_opt_clks_needed(ddata)) {
1206 error = sysc_enable_opt_clocks(ddata);
1207 if (error)
1208 goto err_allow_idle;
1209 }
1210
1211 error = sysc_enable_main_clocks(ddata);
1212 if (error)
1213 goto err_opt_clocks;
1214
1215 if (ddata->legacy_mode) {
1216 error = sysc_runtime_resume_legacy(dev, ddata);
1217 if (error)
1218 goto err_main_clocks;
1219 } else {
1220 error = sysc_enable_module(dev);
1221 if (error)
1222 goto err_main_clocks;
1223 }
1224
1225 ddata->enabled = true;
1226
1227 sysc_clkdm_allow_idle(ddata);
1228
1229 return 0;
1230
1231 err_main_clocks:
1232 sysc_disable_main_clocks(ddata);
1233 err_opt_clocks:
1234 if (sysc_opt_clks_needed(ddata))
1235 sysc_disable_opt_clocks(ddata);
1236 err_allow_idle:
1237 sysc_clkdm_allow_idle(ddata);
1238
1239 return error;
1240 }
1241
1242 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1243 {
1244 struct sysc *ddata;
1245
1246 ddata = dev_get_drvdata(dev);
1247
1248 if (ddata->cfg.quirks &
1249 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1250 return 0;
1251
1252 return pm_runtime_force_suspend(dev);
1253 }
1254
1255 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1256 {
1257 struct sysc *ddata;
1258
1259 ddata = dev_get_drvdata(dev);
1260
1261 if (ddata->cfg.quirks &
1262 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1263 return 0;
1264
1265 return pm_runtime_force_resume(dev);
1266 }
1267
1268 static const struct dev_pm_ops sysc_pm_ops = {
1269 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1270 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1271 sysc_runtime_resume,
1272 NULL)
1273 };
1274
1275 /* Module revision register based quirks */
1276 struct sysc_revision_quirk {
1277 const char *name;
1278 u32 base;
1279 int rev_offset;
1280 int sysc_offset;
1281 int syss_offset;
1282 u32 revision;
1283 u32 revision_mask;
1284 u32 quirks;
1285 };
1286
1287 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1288 optrev_val, optrevmask, optquirkmask) \
1289 { \
1290 .name = (optname), \
1291 .base = (optbase), \
1292 .rev_offset = (optrev), \
1293 .sysc_offset = (optsysc), \
1294 .syss_offset = (optsyss), \
1295 .revision = (optrev_val), \
1296 .revision_mask = (optrevmask), \
1297 .quirks = (optquirkmask), \
1298 }
1299
1300 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1301 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1302 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1303 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1304 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1305 SYSC_QUIRK_LEGACY_IDLE),
1306 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1307 SYSC_QUIRK_LEGACY_IDLE),
1308 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1309 SYSC_QUIRK_LEGACY_IDLE),
1310 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
1311 SYSC_QUIRK_LEGACY_IDLE),
1312 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
1313 SYSC_QUIRK_LEGACY_IDLE),
1314 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1315 0),
1316 /* Some timers on omap4 and later */
1317 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff,
1318 0),
1319 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff,
1320 0),
1321 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1322 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1323 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1324 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1325 /* Uarts on omap4 and later */
1326 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1327 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1328 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1329 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1330
1331 /* Quirks that need to be set based on the module address */
1332 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1333 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1334 SYSC_QUIRK_SWSUP_SIDLE),
1335
1336 /* Quirks that need to be set based on detected module */
1337 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1338 SYSC_MODULE_QUIRK_AESS),
1339 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1340 SYSC_QUIRK_CLKDM_NOAUTO),
1341 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1342 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1343 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1344 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1345 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1346 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1347 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1348 SYSC_QUIRK_CLKDM_NOAUTO),
1349 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1350 SYSC_QUIRK_CLKDM_NOAUTO),
1351 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1352 SYSC_QUIRK_OPT_CLKS_NEEDED),
1353 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1354 SYSC_MODULE_QUIRK_HDQ1W),
1355 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1356 SYSC_MODULE_QUIRK_HDQ1W),
1357 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1358 SYSC_MODULE_QUIRK_I2C),
1359 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1360 SYSC_MODULE_QUIRK_I2C),
1361 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1362 SYSC_MODULE_QUIRK_I2C),
1363 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1364 SYSC_MODULE_QUIRK_I2C),
1365 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1366 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1367 SYSC_MODULE_QUIRK_SGX),
1368 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1369 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1370 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1371 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1372 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1373 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1374 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1375 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1376 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1377 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1378 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1379 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1380 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1381 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1382 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1383 SYSC_MODULE_QUIRK_WDT),
1384 /* Watchdog on am3 and am4 */
1385 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1386 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1387
1388 #ifdef DEBUG
1389 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1390 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1391 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1392 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1393 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1394 0xffff00f0, 0),
1395 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1396 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1397 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1398 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1399 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1400 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1401 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1402 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1403 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1404 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1405 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1406 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1407 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1408 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1409 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1410 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1411 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1412 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1413 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1414 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 0),
1415 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1416 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1417 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1418 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1419 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1420 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1421 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1422 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1423 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1424 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1425 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1426 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1427 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1428 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1429 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1430 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1431 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1432 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1433 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1434 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1435 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1436 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1437 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1438 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1439 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1440 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1441 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1442 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1443 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1444 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1445 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1446 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1447 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1448 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1449 #endif
1450 };
1451
1452 /*
1453 * Early quirks based on module base and register offsets only that are
1454 * needed before the module revision can be read
1455 */
1456 static void sysc_init_early_quirks(struct sysc *ddata)
1457 {
1458 const struct sysc_revision_quirk *q;
1459 int i;
1460
1461 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1462 q = &sysc_revision_quirks[i];
1463
1464 if (!q->base)
1465 continue;
1466
1467 if (q->base != ddata->module_pa)
1468 continue;
1469
1470 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1471 continue;
1472
1473 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1474 continue;
1475
1476 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1477 continue;
1478
1479 ddata->name = q->name;
1480 ddata->cfg.quirks |= q->quirks;
1481 }
1482 }
1483
1484 /* Quirks that also consider the revision register value */
1485 static void sysc_init_revision_quirks(struct sysc *ddata)
1486 {
1487 const struct sysc_revision_quirk *q;
1488 int i;
1489
1490 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1491 q = &sysc_revision_quirks[i];
1492
1493 if (q->base && q->base != ddata->module_pa)
1494 continue;
1495
1496 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1497 continue;
1498
1499 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1500 continue;
1501
1502 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1503 continue;
1504
1505 if (q->revision == ddata->revision ||
1506 (q->revision & q->revision_mask) ==
1507 (ddata->revision & q->revision_mask)) {
1508 ddata->name = q->name;
1509 ddata->cfg.quirks |= q->quirks;
1510 }
1511 }
1512 }
1513
1514 /* 1-wire needs module's internal clocks enabled for reset */
1515 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1516 {
1517 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1518 u16 val;
1519
1520 val = sysc_read(ddata, offset);
1521 val |= BIT(5);
1522 sysc_write(ddata, offset, val);
1523 }
1524
1525 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1526 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1527 {
1528 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1529
1530 sysc_write(ddata, offset, 1);
1531 }
1532
1533 /* I2C needs to be disabled for reset */
1534 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1535 {
1536 int offset;
1537 u16 val;
1538
1539 /* I2C_CON, omap2/3 is different from omap4 and later */
1540 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1541 offset = 0x24;
1542 else
1543 offset = 0xa4;
1544
1545 /* I2C_EN */
1546 val = sysc_read(ddata, offset);
1547 if (enable)
1548 val |= BIT(15);
1549 else
1550 val &= ~BIT(15);
1551 sysc_write(ddata, offset, val);
1552 }
1553
1554 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1555 {
1556 sysc_clk_quirk_i2c(ddata, false);
1557 }
1558
1559 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1560 {
1561 sysc_clk_quirk_i2c(ddata, true);
1562 }
1563
1564 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1565 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1566 {
1567 u32 val, kick0_val = 0, kick1_val = 0;
1568 unsigned long flags;
1569 int error;
1570
1571 if (!lock) {
1572 kick0_val = 0x83e70b13;
1573 kick1_val = 0x95a4f1e0;
1574 }
1575
1576 local_irq_save(flags);
1577 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1578 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1579 !(val & BIT(0)), 100, 50);
1580 if (error)
1581 dev_warn(ddata->dev, "rtc busy timeout\n");
1582 /* Now we have ~15 microseconds to read/write various registers */
1583 sysc_write(ddata, 0x6c, kick0_val);
1584 sysc_write(ddata, 0x70, kick1_val);
1585 local_irq_restore(flags);
1586 }
1587
1588 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1589 {
1590 sysc_quirk_rtc(ddata, false);
1591 }
1592
1593 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1594 {
1595 sysc_quirk_rtc(ddata, true);
1596 }
1597
1598 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1599 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1600 {
1601 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1602 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1603
1604 sysc_write(ddata, offset, val);
1605 }
1606
1607 /* Watchdog timer needs a disable sequence after reset */
1608 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1609 {
1610 int wps, spr, error;
1611 u32 val;
1612
1613 wps = 0x34;
1614 spr = 0x48;
1615
1616 sysc_write(ddata, spr, 0xaaaa);
1617 error = readl_poll_timeout(ddata->module_va + wps, val,
1618 !(val & 0x10), 100,
1619 MAX_MODULE_SOFTRESET_WAIT);
1620 if (error)
1621 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1622
1623 sysc_write(ddata, spr, 0x5555);
1624 error = readl_poll_timeout(ddata->module_va + wps, val,
1625 !(val & 0x10), 100,
1626 MAX_MODULE_SOFTRESET_WAIT);
1627 if (error)
1628 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1629 }
1630
1631 static void sysc_init_module_quirks(struct sysc *ddata)
1632 {
1633 if (ddata->legacy_mode || !ddata->name)
1634 return;
1635
1636 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1637 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1638
1639 return;
1640 }
1641
1642 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1643 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1644 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
1645
1646 return;
1647 }
1648
1649 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1650 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1651
1652 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1653 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1654 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1655
1656 return;
1657 }
1658
1659 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1660 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1661
1662 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1663 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1664 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1665 }
1666 }
1667
1668 static int sysc_clockdomain_init(struct sysc *ddata)
1669 {
1670 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1671 struct clk *fck = NULL, *ick = NULL;
1672 int error;
1673
1674 if (!pdata || !pdata->init_clockdomain)
1675 return 0;
1676
1677 switch (ddata->nr_clocks) {
1678 case 2:
1679 ick = ddata->clocks[SYSC_ICK];
1680 /* fallthrough */
1681 case 1:
1682 fck = ddata->clocks[SYSC_FCK];
1683 break;
1684 case 0:
1685 return 0;
1686 }
1687
1688 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1689 if (!error || error == -ENODEV)
1690 return 0;
1691
1692 return error;
1693 }
1694
1695 /*
1696 * Note that pdata->init_module() typically does a reset first. After
1697 * pdata->init_module() is done, PM runtime can be used for the interconnect
1698 * target module.
1699 */
1700 static int sysc_legacy_init(struct sysc *ddata)
1701 {
1702 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1703 int error;
1704
1705 if (!pdata || !pdata->init_module)
1706 return 0;
1707
1708 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1709 if (error == -EEXIST)
1710 error = 0;
1711
1712 return error;
1713 }
1714
1715 /**
1716 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1717 * @ddata: device driver data
1718 * @reset: reset before deassert
1719 *
1720 * A module can have both OCP softreset control and external rstctrl.
1721 * If more complicated rstctrl resets are needed, please handle these
1722 * directly from the child device driver and map only the module reset
1723 * for the parent interconnect target module device.
1724 *
1725 * Automatic reset of the module on init can be skipped with the
1726 * "ti,no-reset-on-init" device tree property.
1727 */
1728 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1729 {
1730 int error;
1731
1732 if (!ddata->rsts)
1733 return 0;
1734
1735 if (reset) {
1736 error = reset_control_assert(ddata->rsts);
1737 if (error)
1738 return error;
1739 }
1740
1741 reset_control_deassert(ddata->rsts);
1742
1743 return 0;
1744 }
1745
1746 /*
1747 * Note that the caller must ensure the interconnect target module is enabled
1748 * before calling reset. Otherwise reset will not complete.
1749 */
1750 static int sysc_reset(struct sysc *ddata)
1751 {
1752 int sysc_offset, sysc_val, error;
1753 u32 sysc_mask;
1754
1755 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1756
1757 if (ddata->legacy_mode || sysc_offset < 0 ||
1758 ddata->cap->regbits->srst_shift < 0 ||
1759 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1760 return 0;
1761
1762 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1763
1764 if (ddata->pre_reset_quirk)
1765 ddata->pre_reset_quirk(ddata);
1766
1767 sysc_val = sysc_read_sysconfig(ddata);
1768 sysc_val |= sysc_mask;
1769 sysc_write(ddata, sysc_offset, sysc_val);
1770
1771 if (ddata->cfg.srst_udelay)
1772 usleep_range(ddata->cfg.srst_udelay,
1773 ddata->cfg.srst_udelay * 2);
1774
1775 if (ddata->post_reset_quirk)
1776 ddata->post_reset_quirk(ddata);
1777
1778 error = sysc_wait_softreset(ddata);
1779 if (error)
1780 dev_warn(ddata->dev, "OCP softreset timed out\n");
1781
1782 if (ddata->reset_done_quirk)
1783 ddata->reset_done_quirk(ddata);
1784
1785 return error;
1786 }
1787
1788 /*
1789 * At this point the module is configured enough to read the revision but
1790 * module may not be completely configured yet to use PM runtime. Enable
1791 * all clocks directly during init to configure the quirks needed for PM
1792 * runtime based on the revision register.
1793 */
1794 static int sysc_init_module(struct sysc *ddata)
1795 {
1796 int error = 0;
1797 bool manage_clocks = true;
1798
1799 error = sysc_rstctrl_reset_deassert(ddata, false);
1800 if (error)
1801 return error;
1802
1803 if (ddata->cfg.quirks &
1804 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1805 manage_clocks = false;
1806
1807 error = sysc_clockdomain_init(ddata);
1808 if (error)
1809 return error;
1810
1811 sysc_clkdm_deny_idle(ddata);
1812
1813 /*
1814 * Always enable clocks. The bootloader may or may not have enabled
1815 * the related clocks.
1816 */
1817 error = sysc_enable_opt_clocks(ddata);
1818 if (error)
1819 return error;
1820
1821 error = sysc_enable_main_clocks(ddata);
1822 if (error)
1823 goto err_opt_clocks;
1824
1825 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1826 error = sysc_rstctrl_reset_deassert(ddata, true);
1827 if (error)
1828 goto err_main_clocks;
1829 }
1830
1831 ddata->revision = sysc_read_revision(ddata);
1832 sysc_init_revision_quirks(ddata);
1833 sysc_init_module_quirks(ddata);
1834
1835 if (ddata->legacy_mode) {
1836 error = sysc_legacy_init(ddata);
1837 if (error)
1838 goto err_main_clocks;
1839 }
1840
1841 if (!ddata->legacy_mode) {
1842 error = sysc_enable_module(ddata->dev);
1843 if (error)
1844 goto err_main_clocks;
1845 }
1846
1847 error = sysc_reset(ddata);
1848 if (error)
1849 dev_err(ddata->dev, "Reset failed with %d\n", error);
1850
1851 if (!ddata->legacy_mode && manage_clocks)
1852 sysc_disable_module(ddata->dev);
1853
1854 err_main_clocks:
1855 if (manage_clocks)
1856 sysc_disable_main_clocks(ddata);
1857 err_opt_clocks:
1858 /* No re-enable of clockdomain autoidle to prevent module autoidle */
1859 if (manage_clocks) {
1860 sysc_disable_opt_clocks(ddata);
1861 sysc_clkdm_allow_idle(ddata);
1862 }
1863
1864 return error;
1865 }
1866
1867 static int sysc_init_sysc_mask(struct sysc *ddata)
1868 {
1869 struct device_node *np = ddata->dev->of_node;
1870 int error;
1871 u32 val;
1872
1873 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1874 if (error)
1875 return 0;
1876
1877 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1878
1879 return 0;
1880 }
1881
1882 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1883 const char *name)
1884 {
1885 struct device_node *np = ddata->dev->of_node;
1886 struct property *prop;
1887 const __be32 *p;
1888 u32 val;
1889
1890 of_property_for_each_u32(np, name, prop, p, val) {
1891 if (val >= SYSC_NR_IDLEMODES) {
1892 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1893 return -EINVAL;
1894 }
1895 *idlemodes |= (1 << val);
1896 }
1897
1898 return 0;
1899 }
1900
1901 static int sysc_init_idlemodes(struct sysc *ddata)
1902 {
1903 int error;
1904
1905 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1906 "ti,sysc-midle");
1907 if (error)
1908 return error;
1909
1910 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1911 "ti,sysc-sidle");
1912 if (error)
1913 return error;
1914
1915 return 0;
1916 }
1917
1918 /*
1919 * Only some devices on omap4 and later have SYSCONFIG reset done
1920 * bit. We can detect this if there is no SYSSTATUS at all, or the
1921 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1922 * have multiple bits for the child devices like OHCI and EHCI.
1923 * Depends on SYSC being parsed first.
1924 */
1925 static int sysc_init_syss_mask(struct sysc *ddata)
1926 {
1927 struct device_node *np = ddata->dev->of_node;
1928 int error;
1929 u32 val;
1930
1931 error = of_property_read_u32(np, "ti,syss-mask", &val);
1932 if (error) {
1933 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1934 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1935 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1936 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1937
1938 return 0;
1939 }
1940
1941 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1942 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1943
1944 ddata->cfg.syss_mask = val;
1945
1946 return 0;
1947 }
1948
1949 /*
1950 * Many child device drivers need to have fck and opt clocks available
1951 * to get the clock rate for device internal configuration etc.
1952 */
1953 static int sysc_child_add_named_clock(struct sysc *ddata,
1954 struct device *child,
1955 const char *name)
1956 {
1957 struct clk *clk;
1958 struct clk_lookup *l;
1959 int error = 0;
1960
1961 if (!name)
1962 return 0;
1963
1964 clk = clk_get(child, name);
1965 if (!IS_ERR(clk)) {
1966 clk_put(clk);
1967
1968 return -EEXIST;
1969 }
1970
1971 clk = clk_get(ddata->dev, name);
1972 if (IS_ERR(clk))
1973 return -ENODEV;
1974
1975 l = clkdev_create(clk, name, dev_name(child));
1976 if (!l)
1977 error = -ENOMEM;
1978
1979 clk_put(clk);
1980
1981 return error;
1982 }
1983
1984 static int sysc_child_add_clocks(struct sysc *ddata,
1985 struct device *child)
1986 {
1987 int i, error;
1988
1989 for (i = 0; i < ddata->nr_clocks; i++) {
1990 error = sysc_child_add_named_clock(ddata,
1991 child,
1992 ddata->clock_roles[i]);
1993 if (error && error != -EEXIST) {
1994 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1995 ddata->clock_roles[i], error);
1996
1997 return error;
1998 }
1999 }
2000
2001 return 0;
2002 }
2003
2004 static struct device_type sysc_device_type = {
2005 };
2006
2007 static struct sysc *sysc_child_to_parent(struct device *dev)
2008 {
2009 struct device *parent = dev->parent;
2010
2011 if (!parent || parent->type != &sysc_device_type)
2012 return NULL;
2013
2014 return dev_get_drvdata(parent);
2015 }
2016
2017 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2018 {
2019 struct sysc *ddata;
2020 int error;
2021
2022 ddata = sysc_child_to_parent(dev);
2023
2024 error = pm_generic_runtime_suspend(dev);
2025 if (error)
2026 return error;
2027
2028 if (!ddata->enabled)
2029 return 0;
2030
2031 return sysc_runtime_suspend(ddata->dev);
2032 }
2033
2034 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2035 {
2036 struct sysc *ddata;
2037 int error;
2038
2039 ddata = sysc_child_to_parent(dev);
2040
2041 if (!ddata->enabled) {
2042 error = sysc_runtime_resume(ddata->dev);
2043 if (error < 0)
2044 dev_err(ddata->dev,
2045 "%s error: %i\n", __func__, error);
2046 }
2047
2048 return pm_generic_runtime_resume(dev);
2049 }
2050
2051 #ifdef CONFIG_PM_SLEEP
2052 static int sysc_child_suspend_noirq(struct device *dev)
2053 {
2054 struct sysc *ddata;
2055 int error;
2056
2057 ddata = sysc_child_to_parent(dev);
2058
2059 dev_dbg(ddata->dev, "%s %s\n", __func__,
2060 ddata->name ? ddata->name : "");
2061
2062 error = pm_generic_suspend_noirq(dev);
2063 if (error) {
2064 dev_err(dev, "%s error at %i: %i\n",
2065 __func__, __LINE__, error);
2066
2067 return error;
2068 }
2069
2070 if (!pm_runtime_status_suspended(dev)) {
2071 error = pm_generic_runtime_suspend(dev);
2072 if (error) {
2073 dev_dbg(dev, "%s busy at %i: %i\n",
2074 __func__, __LINE__, error);
2075
2076 return 0;
2077 }
2078
2079 error = sysc_runtime_suspend(ddata->dev);
2080 if (error) {
2081 dev_err(dev, "%s error at %i: %i\n",
2082 __func__, __LINE__, error);
2083
2084 return error;
2085 }
2086
2087 ddata->child_needs_resume = true;
2088 }
2089
2090 return 0;
2091 }
2092
2093 static int sysc_child_resume_noirq(struct device *dev)
2094 {
2095 struct sysc *ddata;
2096 int error;
2097
2098 ddata = sysc_child_to_parent(dev);
2099
2100 dev_dbg(ddata->dev, "%s %s\n", __func__,
2101 ddata->name ? ddata->name : "");
2102
2103 if (ddata->child_needs_resume) {
2104 ddata->child_needs_resume = false;
2105
2106 error = sysc_runtime_resume(ddata->dev);
2107 if (error)
2108 dev_err(ddata->dev,
2109 "%s runtime resume error: %i\n",
2110 __func__, error);
2111
2112 error = pm_generic_runtime_resume(dev);
2113 if (error)
2114 dev_err(ddata->dev,
2115 "%s generic runtime resume: %i\n",
2116 __func__, error);
2117 }
2118
2119 return pm_generic_resume_noirq(dev);
2120 }
2121 #endif
2122
2123 static struct dev_pm_domain sysc_child_pm_domain = {
2124 .ops = {
2125 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2126 sysc_child_runtime_resume,
2127 NULL)
2128 USE_PLATFORM_PM_SLEEP_OPS
2129 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2130 sysc_child_resume_noirq)
2131 }
2132 };
2133
2134 /**
2135 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2136 * @ddata: device driver data
2137 * @child: child device driver
2138 *
2139 * Allow idle for child devices as done with _od_runtime_suspend().
2140 * Otherwise many child devices will not idle because of the permanent
2141 * parent usecount set in pm_runtime_irq_safe().
2142 *
2143 * Note that the long term solution is to just modify the child device
2144 * drivers to not set pm_runtime_irq_safe() and then this can be just
2145 * dropped.
2146 */
2147 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2148 {
2149 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2150 dev_pm_domain_set(child, &sysc_child_pm_domain);
2151 }
2152
2153 static int sysc_notifier_call(struct notifier_block *nb,
2154 unsigned long event, void *device)
2155 {
2156 struct device *dev = device;
2157 struct sysc *ddata;
2158 int error;
2159
2160 ddata = sysc_child_to_parent(dev);
2161 if (!ddata)
2162 return NOTIFY_DONE;
2163
2164 switch (event) {
2165 case BUS_NOTIFY_ADD_DEVICE:
2166 error = sysc_child_add_clocks(ddata, dev);
2167 if (error)
2168 return error;
2169 sysc_legacy_idle_quirk(ddata, dev);
2170 break;
2171 default:
2172 break;
2173 }
2174
2175 return NOTIFY_DONE;
2176 }
2177
2178 static struct notifier_block sysc_nb = {
2179 .notifier_call = sysc_notifier_call,
2180 };
2181
2182 /* Device tree configured quirks */
2183 struct sysc_dts_quirk {
2184 const char *name;
2185 u32 mask;
2186 };
2187
2188 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2189 { .name = "ti,no-idle-on-init",
2190 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2191 { .name = "ti,no-reset-on-init",
2192 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2193 { .name = "ti,no-idle",
2194 .mask = SYSC_QUIRK_NO_IDLE, },
2195 };
2196
2197 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2198 bool is_child)
2199 {
2200 const struct property *prop;
2201 int i, len;
2202
2203 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2204 const char *name = sysc_dts_quirks[i].name;
2205
2206 prop = of_get_property(np, name, &len);
2207 if (!prop)
2208 continue;
2209
2210 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2211 if (is_child) {
2212 dev_warn(ddata->dev,
2213 "dts flag should be at module level for %s\n",
2214 name);
2215 }
2216 }
2217 }
2218
2219 static int sysc_init_dts_quirks(struct sysc *ddata)
2220 {
2221 struct device_node *np = ddata->dev->of_node;
2222 int error;
2223 u32 val;
2224
2225 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2226
2227 sysc_parse_dts_quirks(ddata, np, false);
2228 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2229 if (!error) {
2230 if (val > 255) {
2231 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2232 val);
2233 }
2234
2235 ddata->cfg.srst_udelay = (u8)val;
2236 }
2237
2238 return 0;
2239 }
2240
2241 static void sysc_unprepare(struct sysc *ddata)
2242 {
2243 int i;
2244
2245 if (!ddata->clocks)
2246 return;
2247
2248 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2249 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2250 clk_unprepare(ddata->clocks[i]);
2251 }
2252 }
2253
2254 /*
2255 * Common sysc register bits found on omap2, also known as type1
2256 */
2257 static const struct sysc_regbits sysc_regbits_omap2 = {
2258 .dmadisable_shift = -ENODEV,
2259 .midle_shift = 12,
2260 .sidle_shift = 3,
2261 .clkact_shift = 8,
2262 .emufree_shift = 5,
2263 .enwkup_shift = 2,
2264 .srst_shift = 1,
2265 .autoidle_shift = 0,
2266 };
2267
2268 static const struct sysc_capabilities sysc_omap2 = {
2269 .type = TI_SYSC_OMAP2,
2270 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2271 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2272 SYSC_OMAP2_AUTOIDLE,
2273 .regbits = &sysc_regbits_omap2,
2274 };
2275
2276 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2277 static const struct sysc_capabilities sysc_omap2_timer = {
2278 .type = TI_SYSC_OMAP2_TIMER,
2279 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2280 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2281 SYSC_OMAP2_AUTOIDLE,
2282 .regbits = &sysc_regbits_omap2,
2283 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2284 };
2285
2286 /*
2287 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2288 * with different sidle position
2289 */
2290 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2291 .dmadisable_shift = -ENODEV,
2292 .midle_shift = -ENODEV,
2293 .sidle_shift = 4,
2294 .clkact_shift = -ENODEV,
2295 .enwkup_shift = -ENODEV,
2296 .srst_shift = 1,
2297 .autoidle_shift = 0,
2298 .emufree_shift = -ENODEV,
2299 };
2300
2301 static const struct sysc_capabilities sysc_omap3_sham = {
2302 .type = TI_SYSC_OMAP3_SHAM,
2303 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2304 .regbits = &sysc_regbits_omap3_sham,
2305 };
2306
2307 /*
2308 * AES register bits found on omap3 and later, a variant of
2309 * sysc_regbits_omap2 with different sidle position
2310 */
2311 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2312 .dmadisable_shift = -ENODEV,
2313 .midle_shift = -ENODEV,
2314 .sidle_shift = 6,
2315 .clkact_shift = -ENODEV,
2316 .enwkup_shift = -ENODEV,
2317 .srst_shift = 1,
2318 .autoidle_shift = 0,
2319 .emufree_shift = -ENODEV,
2320 };
2321
2322 static const struct sysc_capabilities sysc_omap3_aes = {
2323 .type = TI_SYSC_OMAP3_AES,
2324 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2325 .regbits = &sysc_regbits_omap3_aes,
2326 };
2327
2328 /*
2329 * Common sysc register bits found on omap4, also known as type2
2330 */
2331 static const struct sysc_regbits sysc_regbits_omap4 = {
2332 .dmadisable_shift = 16,
2333 .midle_shift = 4,
2334 .sidle_shift = 2,
2335 .clkact_shift = -ENODEV,
2336 .enwkup_shift = -ENODEV,
2337 .emufree_shift = 1,
2338 .srst_shift = 0,
2339 .autoidle_shift = -ENODEV,
2340 };
2341
2342 static const struct sysc_capabilities sysc_omap4 = {
2343 .type = TI_SYSC_OMAP4,
2344 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2345 SYSC_OMAP4_SOFTRESET,
2346 .regbits = &sysc_regbits_omap4,
2347 };
2348
2349 static const struct sysc_capabilities sysc_omap4_timer = {
2350 .type = TI_SYSC_OMAP4_TIMER,
2351 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2352 SYSC_OMAP4_SOFTRESET,
2353 .regbits = &sysc_regbits_omap4,
2354 };
2355
2356 /*
2357 * Common sysc register bits found on omap4, also known as type3
2358 */
2359 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2360 .dmadisable_shift = -ENODEV,
2361 .midle_shift = 2,
2362 .sidle_shift = 0,
2363 .clkact_shift = -ENODEV,
2364 .enwkup_shift = -ENODEV,
2365 .srst_shift = -ENODEV,
2366 .emufree_shift = -ENODEV,
2367 .autoidle_shift = -ENODEV,
2368 };
2369
2370 static const struct sysc_capabilities sysc_omap4_simple = {
2371 .type = TI_SYSC_OMAP4_SIMPLE,
2372 .regbits = &sysc_regbits_omap4_simple,
2373 };
2374
2375 /*
2376 * SmartReflex sysc found on omap34xx
2377 */
2378 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2379 .dmadisable_shift = -ENODEV,
2380 .midle_shift = -ENODEV,
2381 .sidle_shift = -ENODEV,
2382 .clkact_shift = 20,
2383 .enwkup_shift = -ENODEV,
2384 .srst_shift = -ENODEV,
2385 .emufree_shift = -ENODEV,
2386 .autoidle_shift = -ENODEV,
2387 };
2388
2389 static const struct sysc_capabilities sysc_34xx_sr = {
2390 .type = TI_SYSC_OMAP34XX_SR,
2391 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2392 .regbits = &sysc_regbits_omap34xx_sr,
2393 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2394 SYSC_QUIRK_LEGACY_IDLE,
2395 };
2396
2397 /*
2398 * SmartReflex sysc found on omap36xx and later
2399 */
2400 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2401 .dmadisable_shift = -ENODEV,
2402 .midle_shift = -ENODEV,
2403 .sidle_shift = 24,
2404 .clkact_shift = -ENODEV,
2405 .enwkup_shift = 26,
2406 .srst_shift = -ENODEV,
2407 .emufree_shift = -ENODEV,
2408 .autoidle_shift = -ENODEV,
2409 };
2410
2411 static const struct sysc_capabilities sysc_36xx_sr = {
2412 .type = TI_SYSC_OMAP36XX_SR,
2413 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2414 .regbits = &sysc_regbits_omap36xx_sr,
2415 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2416 };
2417
2418 static const struct sysc_capabilities sysc_omap4_sr = {
2419 .type = TI_SYSC_OMAP4_SR,
2420 .regbits = &sysc_regbits_omap36xx_sr,
2421 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2422 };
2423
2424 /*
2425 * McASP register bits found on omap4 and later
2426 */
2427 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2428 .dmadisable_shift = -ENODEV,
2429 .midle_shift = -ENODEV,
2430 .sidle_shift = 0,
2431 .clkact_shift = -ENODEV,
2432 .enwkup_shift = -ENODEV,
2433 .srst_shift = -ENODEV,
2434 .emufree_shift = -ENODEV,
2435 .autoidle_shift = -ENODEV,
2436 };
2437
2438 static const struct sysc_capabilities sysc_omap4_mcasp = {
2439 .type = TI_SYSC_OMAP4_MCASP,
2440 .regbits = &sysc_regbits_omap4_mcasp,
2441 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2442 };
2443
2444 /*
2445 * McASP found on dra7 and later
2446 */
2447 static const struct sysc_capabilities sysc_dra7_mcasp = {
2448 .type = TI_SYSC_OMAP4_SIMPLE,
2449 .regbits = &sysc_regbits_omap4_simple,
2450 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2451 };
2452
2453 /*
2454 * FS USB host found on omap4 and later
2455 */
2456 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2457 .dmadisable_shift = -ENODEV,
2458 .midle_shift = -ENODEV,
2459 .sidle_shift = 24,
2460 .clkact_shift = -ENODEV,
2461 .enwkup_shift = 26,
2462 .srst_shift = -ENODEV,
2463 .emufree_shift = -ENODEV,
2464 .autoidle_shift = -ENODEV,
2465 };
2466
2467 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2468 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2469 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2470 .regbits = &sysc_regbits_omap4_usb_host_fs,
2471 };
2472
2473 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2474 .dmadisable_shift = -ENODEV,
2475 .midle_shift = -ENODEV,
2476 .sidle_shift = -ENODEV,
2477 .clkact_shift = -ENODEV,
2478 .enwkup_shift = 4,
2479 .srst_shift = 0,
2480 .emufree_shift = -ENODEV,
2481 .autoidle_shift = -ENODEV,
2482 };
2483
2484 static const struct sysc_capabilities sysc_dra7_mcan = {
2485 .type = TI_SYSC_DRA7_MCAN,
2486 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2487 .regbits = &sysc_regbits_dra7_mcan,
2488 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2489 };
2490
2491 static int sysc_init_pdata(struct sysc *ddata)
2492 {
2493 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2494 struct ti_sysc_module_data *mdata;
2495
2496 if (!pdata)
2497 return 0;
2498
2499 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2500 if (!mdata)
2501 return -ENOMEM;
2502
2503 if (ddata->legacy_mode) {
2504 mdata->name = ddata->legacy_mode;
2505 mdata->module_pa = ddata->module_pa;
2506 mdata->module_size = ddata->module_size;
2507 mdata->offsets = ddata->offsets;
2508 mdata->nr_offsets = SYSC_MAX_REGS;
2509 mdata->cap = ddata->cap;
2510 mdata->cfg = &ddata->cfg;
2511 }
2512
2513 ddata->mdata = mdata;
2514
2515 return 0;
2516 }
2517
2518 static int sysc_init_match(struct sysc *ddata)
2519 {
2520 const struct sysc_capabilities *cap;
2521
2522 cap = of_device_get_match_data(ddata->dev);
2523 if (!cap)
2524 return -EINVAL;
2525
2526 ddata->cap = cap;
2527 if (ddata->cap)
2528 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2529
2530 return 0;
2531 }
2532
2533 static void ti_sysc_idle(struct work_struct *work)
2534 {
2535 struct sysc *ddata;
2536
2537 ddata = container_of(work, struct sysc, idle_work.work);
2538
2539 /*
2540 * One time decrement of clock usage counts if left on from init.
2541 * Note that we disable opt clocks unconditionally in this case
2542 * as they are enabled unconditionally during init without
2543 * considering sysc_opt_clks_needed() at that point.
2544 */
2545 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2546 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2547 sysc_disable_main_clocks(ddata);
2548 sysc_disable_opt_clocks(ddata);
2549 sysc_clkdm_allow_idle(ddata);
2550 }
2551
2552 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2553 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2554 return;
2555
2556 /*
2557 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2558 * and SYSC_QUIRK_NO_RESET_ON_INIT
2559 */
2560 if (pm_runtime_active(ddata->dev))
2561 pm_runtime_put_sync(ddata->dev);
2562 }
2563
2564 static const struct of_device_id sysc_match_table[] = {
2565 { .compatible = "simple-bus", },
2566 { /* sentinel */ },
2567 };
2568
2569 static int sysc_probe(struct platform_device *pdev)
2570 {
2571 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2572 struct sysc *ddata;
2573 int error;
2574
2575 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2576 if (!ddata)
2577 return -ENOMEM;
2578
2579 ddata->dev = &pdev->dev;
2580 platform_set_drvdata(pdev, ddata);
2581
2582 error = sysc_init_match(ddata);
2583 if (error)
2584 return error;
2585
2586 error = sysc_init_dts_quirks(ddata);
2587 if (error)
2588 return error;
2589
2590 error = sysc_map_and_check_registers(ddata);
2591 if (error)
2592 return error;
2593
2594 error = sysc_init_sysc_mask(ddata);
2595 if (error)
2596 return error;
2597
2598 error = sysc_init_idlemodes(ddata);
2599 if (error)
2600 return error;
2601
2602 error = sysc_init_syss_mask(ddata);
2603 if (error)
2604 return error;
2605
2606 error = sysc_init_pdata(ddata);
2607 if (error)
2608 return error;
2609
2610 sysc_init_early_quirks(ddata);
2611
2612 error = sysc_get_clocks(ddata);
2613 if (error)
2614 return error;
2615
2616 error = sysc_init_resets(ddata);
2617 if (error)
2618 goto unprepare;
2619
2620 error = sysc_init_module(ddata);
2621 if (error)
2622 goto unprepare;
2623
2624 pm_runtime_enable(ddata->dev);
2625 error = pm_runtime_get_sync(ddata->dev);
2626 if (error < 0) {
2627 pm_runtime_put_noidle(ddata->dev);
2628 pm_runtime_disable(ddata->dev);
2629 goto unprepare;
2630 }
2631
2632 /* Balance reset counts */
2633 if (ddata->rsts)
2634 reset_control_assert(ddata->rsts);
2635
2636 sysc_show_registers(ddata);
2637
2638 ddata->dev->type = &sysc_device_type;
2639 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2640 pdata ? pdata->auxdata : NULL,
2641 ddata->dev);
2642 if (error)
2643 goto err;
2644
2645 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2646
2647 /* At least earlycon won't survive without deferred idle */
2648 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2649 SYSC_QUIRK_NO_IDLE_ON_INIT |
2650 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2651 schedule_delayed_work(&ddata->idle_work, 3000);
2652 } else {
2653 pm_runtime_put(&pdev->dev);
2654 }
2655
2656 return 0;
2657
2658 err:
2659 pm_runtime_put_sync(&pdev->dev);
2660 pm_runtime_disable(&pdev->dev);
2661 unprepare:
2662 sysc_unprepare(ddata);
2663
2664 return error;
2665 }
2666
2667 static int sysc_remove(struct platform_device *pdev)
2668 {
2669 struct sysc *ddata = platform_get_drvdata(pdev);
2670 int error;
2671
2672 cancel_delayed_work_sync(&ddata->idle_work);
2673
2674 error = pm_runtime_get_sync(ddata->dev);
2675 if (error < 0) {
2676 pm_runtime_put_noidle(ddata->dev);
2677 pm_runtime_disable(ddata->dev);
2678 goto unprepare;
2679 }
2680
2681 of_platform_depopulate(&pdev->dev);
2682
2683 pm_runtime_put_sync(&pdev->dev);
2684 pm_runtime_disable(&pdev->dev);
2685 reset_control_assert(ddata->rsts);
2686
2687 unprepare:
2688 sysc_unprepare(ddata);
2689
2690 return 0;
2691 }
2692
2693 static const struct of_device_id sysc_match[] = {
2694 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2695 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2696 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2697 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2698 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2699 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2700 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2701 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2702 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2703 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2704 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2705 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2706 { .compatible = "ti,sysc-usb-host-fs",
2707 .data = &sysc_omap4_usb_host_fs, },
2708 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2709 { },
2710 };
2711 MODULE_DEVICE_TABLE(of, sysc_match);
2712
2713 static struct platform_driver sysc_driver = {
2714 .probe = sysc_probe,
2715 .remove = sysc_remove,
2716 .driver = {
2717 .name = "ti-sysc",
2718 .of_match_table = sysc_match,
2719 .pm = &sysc_pm_ops,
2720 },
2721 };
2722
2723 static int __init sysc_init(void)
2724 {
2725 bus_register_notifier(&platform_bus_type, &sysc_nb);
2726
2727 return platform_driver_register(&sysc_driver);
2728 }
2729 module_init(sysc_init);
2730
2731 static void __exit sysc_exit(void)
2732 {
2733 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2734 platform_driver_unregister(&sysc_driver);
2735 }
2736 module_exit(sysc_exit);
2737
2738 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2739 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support