1 Mediatek IPU controller
2 ============================
4 The Mediatek ipu controller provides various clocks to the system.
8 - compatible: Should be one of:
9 - "mediatek,mt8183-ipu_conn", "syscon"
10 - "mediatek,mt8183-ipu_adl", "syscon"
11 - "mediatek,mt8183-ipu_core0", "syscon"
12 - "mediatek,mt8183-ipu_core1", "syscon"
13 - #clock-cells: Must be 1
15 The ipu controller uses the common clk binding from
16 Documentation/devicetree/bindings/clock/clock-bindings.txt
17 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
21 ipu_conn: syscon@19000000 {
22 compatible = "mediatek,mt8183-ipu_conn", "syscon";
23 reg = <0 0x19000000 0 0x1000>;
27 ipu_adl: syscon@19010000 {
28 compatible = "mediatek,mt8183-ipu_adl", "syscon";
29 reg = <0 0x19010000 0 0x1000>;
33 ipu_core0: syscon@19180000 {
34 compatible = "mediatek,mt8183-ipu_core0", "syscon";
35 reg = <0 0x19180000 0 0x1000>;
39 ipu_core1: syscon@19280000 {
40 compatible = "mediatek,mt8183-ipu_core1", "syscon";
41 reg = <0 0x19280000 0 0x1000>;