Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt

   1 Qualcomm Technologies, Inc. CPUFREQ Bindings
   2
   3 CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
   4 SoCs to manage frequency in hardware. It is capable of controlling frequency
   5 for multiple clusters.
   6
   7 Properties:
   8 - compatible
   9         Usage:          required
  10         Value type:     <string>
  11         Definition:     must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
  12
  13 - clocks
  14         Usage:          required
  15         Value type:     <phandle> From common clock binding.
  16         Definition:     clock handle for XO clock and GPLL0 clock.
  17
  18 - clock-names
  19         Usage:          required
  20         Value type:     <string> From common clock binding.
  21         Definition:     must be "xo", "alternate".
  22
  23 - reg
  24         Usage:          required
  25         Value type:     <prop-encoded-array>
  26         Definition:     Addresses and sizes for the memory of the HW bases in
  27                         each frequency domain.
  28 - reg-names
  29         Usage:          Optional
  30         Value type:     <string>
  31         Definition:     Frequency domain name i.e.
  32                         "freq-domain0", "freq-domain1".
  33
  34 - #freq-domain-cells:
  35         Usage:          required.
  36         Definition:     Number of cells in a freqency domain specifier.
  37
  38 * Property qcom,freq-domain
  39 Devices supporting freq-domain must set their "qcom,freq-domain" property with
  40 phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
  41
  42
  43 Example:
  44
  45 Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch
  46 DCVS state together.
  47
  48 / {
  49         cpus {
  50                 #address-cells = <2>;
  51                 #size-cells = <0>;
  52
  53                 CPU0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "qcom,kryo385";
  56                         reg = <0x0 0x0>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&L2_0>;
  59                         qcom,freq-domain = <&cpufreq_hw 0>;
  60                         L2_0: l2-cache {
  61                                 compatible = "cache";
  62                                 next-level-cache = <&L3_0>;
  63                                 L3_0: l3-cache {
  64                                       compatible = "cache";
  65                                 };
  66                         };
  67                 };
  68
  69                 CPU1: cpu@100 {
  70                         device_type = "cpu";
  71                         compatible = "qcom,kryo385";
  72                         reg = <0x0 0x100>;
  73                         enable-method = "psci";
  74                         next-level-cache = <&L2_100>;
  75                         qcom,freq-domain = <&cpufreq_hw 0>;
  76                         L2_100: l2-cache {
  77                                 compatible = "cache";
  78                                 next-level-cache = <&L3_0>;
  79                         };
  80                 };
  81
  82                 CPU2: cpu@200 {
  83                         device_type = "cpu";
  84                         compatible = "qcom,kryo385";
  85                         reg = <0x0 0x200>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&L2_200>;
  88                         qcom,freq-domain = <&cpufreq_hw 0>;
  89                         L2_200: l2-cache {
  90                                 compatible = "cache";
  91                                 next-level-cache = <&L3_0>;
  92                         };
  93                 };
  94
  95                 CPU3: cpu@300 {
  96                         device_type = "cpu";
  97                         compatible = "qcom,kryo385";
  98                         reg = <0x0 0x300>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&L2_300>;
 101                         qcom,freq-domain = <&cpufreq_hw 0>;
 102                         L2_300: l2-cache {
 103                                 compatible = "cache";
 104                                 next-level-cache = <&L3_0>;
 105                         };
 106                 };
 107
 108                 CPU4: cpu@400 {
 109                         device_type = "cpu";
 110                         compatible = "qcom,kryo385";
 111                         reg = <0x0 0x400>;
 112                         enable-method = "psci";
 113                         next-level-cache = <&L2_400>;
 114                         qcom,freq-domain = <&cpufreq_hw 1>;
 115                         L2_400: l2-cache {
 116                                 compatible = "cache";
 117                                 next-level-cache = <&L3_0>;
 118                         };
 119                 };
 120
 121                 CPU5: cpu@500 {
 122                         device_type = "cpu";
 123                         compatible = "qcom,kryo385";
 124                         reg = <0x0 0x500>;
 125                         enable-method = "psci";
 126                         next-level-cache = <&L2_500>;
 127                         qcom,freq-domain = <&cpufreq_hw 1>;
 128                         L2_500: l2-cache {
 129                                 compatible = "cache";
 130                                 next-level-cache = <&L3_0>;
 131                         };
 132                 };
 133
 134                 CPU6: cpu@600 {
 135                         device_type = "cpu";
 136                         compatible = "qcom,kryo385";
 137                         reg = <0x0 0x600>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&L2_600>;
 140                         qcom,freq-domain = <&cpufreq_hw 1>;
 141                         L2_600: l2-cache {
 142                                 compatible = "cache";
 143                                 next-level-cache = <&L3_0>;
 144                         };
 145                 };
 146
 147                 CPU7: cpu@700 {
 148                         device_type = "cpu";
 149                         compatible = "qcom,kryo385";
 150                         reg = <0x0 0x700>;
 151                         enable-method = "psci";
 152                         next-level-cache = <&L2_700>;
 153                         qcom,freq-domain = <&cpufreq_hw 1>;
 154                         L2_700: l2-cache {
 155                                 compatible = "cache";
 156                                 next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159         };
 160
 161  soc {
 162         cpufreq_hw: cpufreq@17d43000 {
 163                 compatible = "qcom,cpufreq-hw";
 164                 reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
 165                 reg-names = "freq-domain0", "freq-domain1";
 166
 167                 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 168                 clock-names = "xo", "alternate";
 169
 170                 #freq-domain-cells = <1>;
 171         };
 172 }