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1 * Generic Exynos Bus frequency device
3 The Samsung Exynos SoC has many buses for data transfer between DRAM
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
6 and a power line, which are able to change the clock frequency
7 of the bus in runtime. To monitor the usage of each bus in runtime,
8 the driver uses the PPMU (Platform Performance Monitoring Unit), which
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
15 There are two type of bus devices as following:
16 - parent bus device
17 - passive bus device
19 Basically, parent and passive bus device share the same power line.
20 The parent bus device can only change the voltage of shared power line
21 and the rest bus devices (passive bus device) depend on the decision of
22 the parent bus device. If there are three blocks which share the VDD_xxx
23 power line, Only one block should be parent device and then the rest blocks
24 should depend on the parent device as passive device.
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
28 |--- C block (passive)
30 There are a little different composition among Exynos SoC because each Exynos
31 SoC has different sub-blocks. Therefore, such difference should be specified
32 in devicetree file instead of each device driver. In result, this driver
33 is able to support the bus frequency for all Exynos SoCs.
35 Required properties for all bus devices:
36 - compatible: Should be "samsung,exynos-bus".
37 - clock-names : the name of clock used by the bus, "bus".
38 - clocks : phandles for clock specified in "clock-names" property.
39 - operating-points-v2: the OPP table including frequency/voltage information
40 to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
42 Required properties only for parent bus device:
43 - vdd-supply: the regulator to provide the buses with the voltage.
44 - devfreq-events: the devfreq-event device to monitor the current utilization
45 of buses.
47 Required properties only for passive bus device:
48 - devfreq: the parent bus device.
50 Optional properties only for parent bus device:
51 - exynos,saturation-ratio: the percentage value which is used to calibrate
52 the performance count against total cycle count.
54 Optional properties for the interconnect functionality (QoS frequency
55 constraints):
56 - #interconnect-cells: should be 0.
57 - interconnects: as documented in ../interconnect.txt, describes a path at the
58 higher level interconnects used by this interconnect provider.
59 If this interconnect provider is directly linked to a top level interconnect
60 provider the property contains only one phandle. The provider extends
61 the interconnect graph by linking its node to a node registered by provider
62 pointed to by first phandle in the 'interconnects' property.
64 - samsung,data-clock-ratio: ratio of the data throughput in B/s to minimum data
65 clock frequency in Hz, default value is 8 when this property is missing.
67 Detailed correlation between sub-blocks and power line according to Exynos SoC:
68 - In case of Exynos3250, there are two power line as following:
69 VDD_MIF |--- DMC
71 VDD_INT |--- LEFTBUS (parent device)
72 |--- PERIL
73 |--- MFC
74 |--- G3D
75 |--- RIGHTBUS
76 |--- PERIR
77 |--- FSYS
78 |--- LCD0
79 |--- PERIR
80 |--- ISP
81 |--- CAM
83 - In case of Exynos4210, there is one power line as following:
84 VDD_INT |--- DMC (parent device)
85 |--- LEFTBUS
86 |--- PERIL
87 |--- MFC(L)
88 |--- G3D
89 |--- TV
90 |--- LCD0
91 |--- RIGHTBUS
92 |--- PERIR
93 |--- MFC(R)
94 |--- CAM
95 |--- FSYS
96 |--- GPS
97 |--- LCD0
98 |--- LCD1
100 - In case of Exynos4x12, there are two power line as following:
101 VDD_MIF |--- DMC
103 VDD_INT |--- LEFTBUS (parent device)
104 |--- PERIL
105 |--- MFC(L)
106 |--- G3D
107 |--- TV
108 |--- IMAGE
109 |--- RIGHTBUS
110 |--- PERIR
111 |--- MFC(R)
112 |--- CAM
113 |--- FSYS
114 |--- GPS
115 |--- LCD0
116 |--- ISP
118 - In case of Exynos5422, there are two power line as following:
119 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
120 |--- DREX 1
122 VDD_INT |--- NoC_Core (parent device)
123 |--- G2D
124 |--- G3D
125 |--- DISP1
126 |--- NoC_WCORE
127 |--- GSCL
128 |--- MSCL
129 |--- ISP
130 |--- MFC
131 |--- GEN
132 |--- PERIS
133 |--- PERIC
134 |--- FSYS
135 |--- FSYS2
137 - In case of Exynos5433, there is VDD_INT power line as following:
138 VDD_INT |--- G2D (parent device)
139 |--- MSCL
140 |--- GSCL
141 |--- JPEG
142 |--- MFC
143 |--- HEVC
144 |--- BUS0
145 |--- BUS1
146 |--- BUS2
147 |--- PERIS (Fixed clock rate)
148 |--- PERIC (Fixed clock rate)
149 |--- FSYS (Fixed clock rate)
151 Example 1:
152 Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
153 power line (regulator). The MIF (Memory Interface) AXI bus is used to
154 transfer data between DRAM and CPU and uses the VDD_MIF regulator.
156 - MIF (Memory Interface) block
157 : VDD_MIF |--- DMC (Dynamic Memory Controller)
159 - INT (Internal) block
160 : VDD_INT |--- LEFTBUS (parent device)
161 |--- PERIL
162 |--- MFC
163 |--- G3D
164 |--- RIGHTBUS
165 |--- FSYS
166 |--- LCD0
167 |--- PERIR
168 |--- ISP
169 |--- CAM
171 - MIF bus's frequency/voltage table
172 -----------------------
173 |Lv| Freq | Voltage |
174 -----------------------
175 |L1| 50000 |800000 |
176 |L2| 100000 |800000 |
177 |L3| 134000 |800000 |
178 |L4| 200000 |825000 |
179 |L5| 400000 |875000 |
180 -----------------------
182 - INT bus's frequency/voltage table
183 ----------------------------------------------------------
184 |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT |
185 | name| |LCD0 | | | || |
186 | | |FSYS | | | || |
187 | | |MFC | | | || |
188 ----------------------------------------------------------
189 |Mode |*parent|passive |passive|passive|passive|| |
190 ----------------------------------------------------------
191 |Lv |Frequency ||Voltage |
192 ----------------------------------------------------------
193 |L1 |50000 |50000 |50000 |50000 |50000 ||900000 |
194 |L2 |80000 |80000 |80000 |80000 |80000 ||900000 |
195 |L3 |100000 |100000 |100000 |100000 |100000 ||1000000 |
196 |L4 |134000 |134000 |200000 |200000 | ||1000000 |
197 |L5 |200000 |200000 |400000 |300000 | ||1000000 |
198 ----------------------------------------------------------
200 Example 2:
201 The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
202 is listed below:
204 bus_dmc: bus_dmc {
205 compatible = "samsung,exynos-bus";
206 clocks = <&cmu_dmc CLK_DIV_DMC>;
207 clock-names = "bus";
208 operating-points-v2 = <&bus_dmc_opp_table>;
209 status = "disabled";
210 };
212 bus_dmc_opp_table: opp_table1 {
213 compatible = "operating-points-v2";
214 opp-shared;
216 opp-50000000 {
217 opp-hz = /bits/ 64 <50000000>;
218 opp-microvolt = <800000>;
219 };
220 opp-100000000 {
221 opp-hz = /bits/ 64 <100000000>;
222 opp-microvolt = <800000>;
223 };
224 opp-134000000 {
225 opp-hz = /bits/ 64 <134000000>;
226 opp-microvolt = <800000>;
227 };
228 opp-200000000 {
229 opp-hz = /bits/ 64 <200000000>;
230 opp-microvolt = <825000>;
231 };
232 opp-400000000 {
233 opp-hz = /bits/ 64 <400000000>;
234 opp-microvolt = <875000>;
235 };
236 };
238 bus_leftbus: bus_leftbus {
239 compatible = "samsung,exynos-bus";
240 clocks = <&cmu CLK_DIV_GDL>;
241 clock-names = "bus";
242 operating-points-v2 = <&bus_leftbus_opp_table>;
243 status = "disabled";
244 };
246 bus_rightbus: bus_rightbus {
247 compatible = "samsung,exynos-bus";
248 clocks = <&cmu CLK_DIV_GDR>;
249 clock-names = "bus";
250 operating-points-v2 = <&bus_leftbus_opp_table>;
251 status = "disabled";
252 };
254 bus_lcd0: bus_lcd0 {
255 compatible = "samsung,exynos-bus";
256 clocks = <&cmu CLK_DIV_ACLK_160>;
257 clock-names = "bus";
258 operating-points-v2 = <&bus_leftbus_opp_table>;
259 status = "disabled";
260 };
262 bus_fsys: bus_fsys {
263 compatible = "samsung,exynos-bus";
264 clocks = <&cmu CLK_DIV_ACLK_200>;
265 clock-names = "bus";
266 operating-points-v2 = <&bus_leftbus_opp_table>;
267 status = "disabled";
268 };
270 bus_mcuisp: bus_mcuisp {
271 compatible = "samsung,exynos-bus";
272 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
273 clock-names = "bus";
274 operating-points-v2 = <&bus_mcuisp_opp_table>;
275 status = "disabled";
276 };
278 bus_isp: bus_isp {
279 compatible = "samsung,exynos-bus";
280 clocks = <&cmu CLK_DIV_ACLK_266>;
281 clock-names = "bus";
282 operating-points-v2 = <&bus_isp_opp_table>;
283 status = "disabled";
284 };
286 bus_peril: bus_peril {
287 compatible = "samsung,exynos-bus";
288 clocks = <&cmu CLK_DIV_ACLK_100>;
289 clock-names = "bus";
290 operating-points-v2 = <&bus_peril_opp_table>;
291 status = "disabled";
292 };
294 bus_mfc: bus_mfc {
295 compatible = "samsung,exynos-bus";
296 clocks = <&cmu CLK_SCLK_MFC>;
297 clock-names = "bus";
298 operating-points-v2 = <&bus_leftbus_opp_table>;
299 status = "disabled";
300 };
302 bus_leftbus_opp_table: opp_table1 {
303 compatible = "operating-points-v2";
304 opp-shared;
306 opp-50000000 {
307 opp-hz = /bits/ 64 <50000000>;
308 opp-microvolt = <900000>;
309 };
310 opp-80000000 {
311 opp-hz = /bits/ 64 <80000000>;
312 opp-microvolt = <900000>;
313 };
314 opp-100000000 {
315 opp-hz = /bits/ 64 <100000000>;
316 opp-microvolt = <1000000>;
317 };
318 opp-134000000 {
319 opp-hz = /bits/ 64 <134000000>;
320 opp-microvolt = <1000000>;
321 };
322 opp-200000000 {
323 opp-hz = /bits/ 64 <200000000>;
324 opp-microvolt = <1000000>;
325 };
326 };
328 bus_mcuisp_opp_table: opp_table2 {
329 compatible = "operating-points-v2";
330 opp-shared;
332 opp-50000000 {
333 opp-hz = /bits/ 64 <50000000>;
334 };
335 opp-80000000 {
336 opp-hz = /bits/ 64 <80000000>;
337 };
338 opp-100000000 {
339 opp-hz = /bits/ 64 <100000000>;
340 };
341 opp-200000000 {
342 opp-hz = /bits/ 64 <200000000>;
343 };
344 opp-400000000 {
345 opp-hz = /bits/ 64 <400000000>;
346 };
347 };
349 bus_isp_opp_table: opp_table3 {
350 compatible = "operating-points-v2";
351 opp-shared;
353 opp-50000000 {
354 opp-hz = /bits/ 64 <50000000>;
355 };
356 opp-80000000 {
357 opp-hz = /bits/ 64 <80000000>;
358 };
359 opp-100000000 {
360 opp-hz = /bits/ 64 <100000000>;
361 };
362 opp-200000000 {
363 opp-hz = /bits/ 64 <200000000>;
364 };
365 opp-300000000 {
366 opp-hz = /bits/ 64 <300000000>;
367 };
368 };
370 bus_peril_opp_table: opp_table4 {
371 compatible = "operating-points-v2";
372 opp-shared;
374 opp-50000000 {
375 opp-hz = /bits/ 64 <50000000>;
376 };
377 opp-80000000 {
378 opp-hz = /bits/ 64 <80000000>;
379 };
380 opp-100000000 {
381 opp-hz = /bits/ 64 <100000000>;
382 };
383 };
386 Usage case to handle the frequency and voltage of bus on runtime
387 in exynos3250-rinato.dts is listed below:
389 &bus_dmc {
390 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
391 vdd-supply = <&buck1_reg>; /* VDD_MIF */
392 status = "okay";
393 };
395 &bus_leftbus {
396 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
397 vdd-supply = <&buck3_reg>;
398 status = "okay";
399 };
401 &bus_rightbus {
402 devfreq = <&bus_leftbus>;
403 status = "okay";
404 };
406 &bus_lcd0 {
407 devfreq = <&bus_leftbus>;
408 status = "okay";
409 };
411 &bus_fsys {
412 devfreq = <&bus_leftbus>;
413 status = "okay";
414 };
416 &bus_mcuisp {
417 devfreq = <&bus_leftbus>;
418 status = "okay";
419 };
421 &bus_isp {
422 devfreq = <&bus_leftbus>;
423 status = "okay";
424 };
426 &bus_peril {
427 devfreq = <&bus_leftbus>;
428 status = "okay";
429 };
431 &bus_mfc {
432 devfreq = <&bus_leftbus>;
433 status = "okay";
434 };
436 Example 3:
437 An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
438 Exynos4412 SoC with video mixer as an interconnect consumer device.
440 soc {
441 bus_dmc: bus_dmc {
442 compatible = "samsung,exynos-bus";
443 clocks = <&clock CLK_DIV_DMC>;
444 clock-names = "bus";
445 operating-points-v2 = <&bus_dmc_opp_table>;
446 samsung,data-clock-ratio = <4>;
447 #interconnect-cells = <0>;
448 };
450 bus_leftbus: bus_leftbus {
451 compatible = "samsung,exynos-bus";
452 clocks = <&clock CLK_DIV_GDL>;
453 clock-names = "bus";
454 operating-points-v2 = <&bus_leftbus_opp_table>;
455 #interconnect-cells = <0>;
456 interconnects = <&bus_dmc>;
457 };
459 bus_display: bus_display {
460 compatible = "samsung,exynos-bus";
461 clocks = <&clock CLK_ACLK160>;
462 clock-names = "bus";
463 operating-points-v2 = <&bus_display_opp_table>;
464 #interconnect-cells = <0>;
465 interconnects = <&bus_leftbus &bus_dmc>;
466 };
468 bus_dmc_opp_table: opp_table1 {
469 compatible = "operating-points-v2";
470 /* ... */
471 }
473 bus_leftbus_opp_table: opp_table3 {
474 compatible = "operating-points-v2";
475 /* ... */
476 };
478 bus_display_opp_table: opp_table4 {
479 compatible = "operating-points-v2";
480 /* .. */
481 };
483 &mixer {
484 compatible = "samsung,exynos4212-mixer";
485 interconnects = <&bus_display &bus_dmc>;
486 /* ... */
487 };
488 };