WIP FPC-III support
[linux/fpc-iii.git] / Documentation / devicetree / bindings / display / arm,pl11x.txt
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1 * ARM PrimeCell Color LCD Controller PL110/PL111
3 See also Documentation/devicetree/bindings/arm/primecell.yaml
5 Required properties:
7 - compatible: must be one of:
8         "arm,pl110", "arm,primecell"
9         "arm,pl111", "arm,primecell"
11 - reg: base address and size of the control registers block
13 - interrupt-names: either the single entry "combined" representing a
14         combined interrupt output (CLCDINTR), or the four entries
15         "mbe", "vcomp", "lnbu", "fuf" representing the individual
16         CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts
18 - interrupts: contains an interrupt specifier for each entry in
19         interrupt-names
21 - clock-names: should contain "clcdclk" and "apb_pclk"
23 - clocks: contains phandle and clock specifier pairs for the entries
24         in the clock-names property. See
25         Documentation/devicetree/bindings/clock/clock-bindings.txt
27 Optional properties:
29 - memory-region: phandle to a node describing memory (see
30         Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
31         to be used for the framebuffer; if not present, the framebuffer
32         may be located anywhere in the memory
34 - max-memory-bandwidth: maximum bandwidth in bytes per second that the
35         cell's memory interface can handle; if not present, the memory
36         interface is fast enough to handle all possible video modes
38 Required sub-nodes:
40 - port: describes LCD panel signals, following the common binding
41         for video transmitter interfaces; see
42         Documentation/devicetree/bindings/media/video-interfaces.txt
44 Deprecated properties:
45         The port's endbpoint subnode had this, now deprecated property
46         in the past. Drivers should be able to survive without it:
48         - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
49                 defining the way CLD pads are wired up; first value
50                 contains index of the "CLD" external pin (pad) used
51                 as R0 (first bit of the red component), second value
52                 index of the pad used as G0, third value index of the
53                 pad used as B0, see also "LCD panel signal multiplexing
54                 details" paragraphs in the PL110/PL111 Technical
55                 Reference Manuals; this implicitly defines available
56                 color modes, for example:
57                 - PL111 TFT 4:4:4 panel:
58                         arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
59                 - PL110 TFT (1:)5:5:5 panel:
60                         arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
61                 - PL111 TFT (1:)5:5:5 panel:
62                         arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
63                 - PL111 TFT 5:6:5 panel:
64                         arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
65                 - PL110 and PL111 TFT 8:8:8 panel:
66                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
67                 - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
68                         arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
71 Example:
73         clcd@10020000 {
74                 compatible = "arm,pl111", "arm,primecell";
75                 reg = <0x10020000 0x1000>;
76                 interrupt-names = "combined";
77                 interrupts = <0 44 4>;
78                 clocks = <&oscclk1>, <&oscclk2>;
79                 clock-names = "clcdclk", "apb_pclk";
80                 max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
82                 port {
83                         clcd_pads: endpoint {
84                                 remote-endpoint = <&clcd_panel>;
85                         };
86                 };
88         };
90         panel {
91                 compatible = "panel-dpi";
93                 port {
94                         clcd_panel: endpoint {
95                                 remote-endpoint = <&clcd_pads>;
96                         };
97                 };
99                 panel-timing {
100                         clock-frequency = <25175000>;
101                         hactive = <640>;
102                         hback-porch = <40>;
103                         hfront-porch = <24>;
104                         hsync-len = <96>;
105                         vactive = <480>;
106                         vback-porch = <32>;
107                         vfront-porch = <11>;
108                         vsync-len = <2>;
109                 };
110         };