1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
24 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
25 The AUX and PMA registers are not part of this range, they are instead
26 included in the associated PHY.
28 Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
40 DP bridge clock, used by the IP to know how to translate a number of
41 clock cycles into a time (which is used to comply with DP standard timings
47 phandle to the DisplayPort PHY.
62 Ports as described in Documentation/devicetree/bindings/graph.txt.
74 First input port representing the DP bridge input.
79 Second input port representing the DP bridge input.
84 Third input port representing the DP bridge input.
89 Fourth input port representing the DP bridge input.
94 Output port representing the DP bridge output.
107 const: ti,j721e-mhdp8546
131 additionalProperties: false
135 #include <dt-bindings/interrupt-controller/arm-gic.h>
137 #address-cells = <2>;
140 mhdp: dp-bridge@f0fb000000 {
141 compatible = "cdns,mhdp8546";
142 reg = <0xf0 0xfb000000 0x0 0x1000000>;
143 reg-names = "mhdptx";
144 clocks = <&mhdp_clock>;
147 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
150 #address-cells = <1>;
155 dp_bridge_input: endpoint {
156 remote-endpoint = <&xxx_dpi_output>;
162 dp_bridge_output: endpoint {
163 remote-endpoint = <&xxx_dp_connector_input>;