1 Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
3 DECON (Display and Enhancement Controller) is the Display Controller for the
4 Exynos7 series of SoCs which transfers the image data from a video memory
5 buffer to an external LCD interface.
8 - compatible: value should be "samsung,exynos7-decon";
10 - reg: physical base address and length of the DECON registers set.
12 - interrupts: should contain a list of all DECON IP block interrupts in the
13 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
14 format depends on the interrupt controller used.
16 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
17 "lcd_sys", in the same order as they were listed in the interrupts
20 - pinctrl-0: pin control group to be used for this controller.
22 - pinctrl-names: must contain a "default" entry.
24 - clocks: must include clock specifiers corresponding to entries in the
27 - clock-names: list of clock names sorted in the same order as the clocks
28 property. Must contain "pclk_decon0", "aclk_decon0",
29 "decon0_eclk", "decon0_vclk".
30 - i80-if-timings: timing configuration for lcd i80 interface support.
33 - power-domains: a phandle to DECON power domain node.
34 - display-timings: timing settings for DECON, as described in document [1].
35 Can be used in case timings cannot be provided otherwise
36 or to override timings provided by the panel.
38 [1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
42 SoC specific DT entry:
45 compatible = "samsung,exynos7-decon";
46 interrupt-parent = <&combiner>;
47 reg = <0x13930000 0x1000>;
48 interrupt-names = "lcd_sys", "vsync", "fifo";
49 interrupts = <0 188 0>, <0 189 0>, <0 190 0>;
50 clocks = <&clock_disp PCLK_DECON_INT>,
51 <&clock_disp ACLK_DECON_INT>,
52 <&clock_disp SCLK_DECON_INT_ECLK>,
53 <&clock_disp SCLK_DECON_INT_EXTCLKPLL>;
54 clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk",
59 Board specific DT entry:
62 pinctrl-0 = <&lcd_clk &pwm1_out>;
63 pinctrl-names = "default";