Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt

   1 Rockchip RK3288 LVDS interface
   2 ================================
   3
   4 Required properties:
   5 - compatible: matching the soc type, one of
   6         - "rockchip,rk3288-lvds";
   7         - "rockchip,px30-lvds";
   8
   9 - reg: physical base address of the controller and length
  10         of memory mapped region.
  11 - clocks: must include clock specifiers corresponding to entries in the
  12         clock-names property.
  13 - clock-names: must contain "pclk_lvds"
  14
  15 - avdd1v0-supply: regulator phandle for 1.0V analog power
  16 - avdd1v8-supply: regulator phandle for 1.8V analog power
  17 - avdd3v3-supply: regulator phandle for 3.3V analog power
  18
  19 - rockchip,grf: phandle to the general register files syscon
  20 - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
  21
  22 - phys: LVDS/DSI DPHY (px30 only)
  23 - phy-names: name of the PHY, must be "dphy" (px30 only)
  24
  25 Optional properties:
  26 - pinctrl-names: must contain a "lcdc" entry.
  27 - pinctrl-0: pin control group to be used for this controller.
  28
  29 Required nodes:
  30
  31 The lvds has two video ports as described by
  32         Documentation/devicetree/bindings/media/video-interfaces.txt
  33 Their connections are modeled using the OF graph bindings specified in
  34         Documentation/devicetree/bindings/graph.txt.
  35
  36 - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
  37 - video port 1 for either a panel or subsequent encoder
  38
  39 Example:
  40
  41 lvds_panel: lvds-panel {
  42         compatible = "auo,b101ean01";
  43         enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
  44         data-mapping = "jeida-24";
  45
  46         ports {
  47                 panel_in_lvds: endpoint {
  48                         remote-endpoint = <&lvds_out_panel>;
  49                 };
  50         };
  51 };
  52
  53 For Rockchip RK3288:
  54
  55         lvds: lvds@ff96c000 {
  56                 compatible = "rockchip,rk3288-lvds";
  57                 rockchip,grf = <&grf>;
  58                 reg = <0xff96c000 0x4000>;
  59                 clocks = <&cru PCLK_LVDS_PHY>;
  60                 clock-names = "pclk_lvds";
  61                 pinctrl-names = "lcdc";
  62                 pinctrl-0 = <&lcdc_ctl>;
  63                 avdd1v0-supply = <&vdd10_lcd>;
  64                 avdd1v8-supply = <&vcc18_lcd>;
  65                 avdd3v3-supply = <&vcca_33>;
  66                 rockchip,output = "rgb";
  67                 ports {
  68                         #address-cells = <1>;
  69                         #size-cells = <0>;
  70
  71                         lvds_in: port@0 {
  72                                 reg = <0>;
  73
  74                                 lvds_in_vopb: endpoint@0 {
  75                                         reg = <0>;
  76                                         remote-endpoint = <&vopb_out_lvds>;
  77                                 };
  78                                 lvds_in_vopl: endpoint@1 {
  79                                         reg = <1>;
  80                                         remote-endpoint = <&vopl_out_lvds>;
  81                                 };
  82                         };
  83
  84                         lvds_out: port@1 {
  85                                 reg = <1>;
  86
  87                                 lvds_out_panel: endpoint {
  88                                         remote-endpoint = <&panel_in_lvds>;
  89                                 };
  90                         };
  91                 };
  92         };