WIP FPC-III support
[linux/fpc-iii.git] / Documentation / devicetree / bindings / dma / owl-dma.yaml
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1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
9 description: |
10   The OWL DMA is a general-purpose direct memory access controller capable of
11   supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
12   respectively.
14 maintainers:
15   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
17 allOf:
18   - $ref: "dma-controller.yaml#"
20 properties:
21   compatible:
22     enum:
23       - actions,s900-dma
24       - actions,s700-dma
26   reg:
27     maxItems: 1
29   interrupts:
30     description:
31       controller supports 4 interrupts, which are freely assignable to the
32       DMA channels.
33     maxItems: 4
35   "#dma-cells":
36     const: 1
38   dma-channels:
39     maximum: 12
41   dma-requests:
42     maximum: 46
44   clocks:
45     maxItems: 1
46     description:
47       Phandle and Specifier of the clock feeding the DMA controller.
49   power-domains:
50     maxItems: 1
52 required:
53   - compatible
54   - reg
55   - interrupts
56   - "#dma-cells"
57   - dma-channels
58   - dma-requests
59   - clocks
61 unevaluatedProperties: false
63 examples:
64   - |
65     #include <dt-bindings/interrupt-controller/arm-gic.h>
66     dma: dma-controller@e0260000 {
67         compatible = "actions,s900-dma";
68         reg = <0xe0260000 0x1000>;
69         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
70                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
71                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
72                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
73         #dma-cells = <1>;
74         dma-channels = <12>;
75         dma-requests = <46>;
76         clocks = <&clock 22>;
77     };
79 ...