Documentation/devicetree/bindings/dma/ti/k3-pktdma.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Texas Instruments Incorporated
   3 # Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   4 %YAML 1.2
   5 ---
   6 $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
   7 $schema: http://devicetree.org/meta-schemas/core.yaml#
   8
   9 title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings
  10
  11 maintainers:
  12   - Peter Ujfalusi <peter.ujfalusi@gmail.com>
  13
  14 description: |
  15   The Packet DMA (PKTDMA) is intended to perform similar functions as the packet
  16   mode channels of K3 UDMA-P.
  17   PKTDMA only includes Split channels to service PSI-L based peripherals.
  18
  19   The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
  20   with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
  21   legacy peripheral.
  22
  23   PDMAs can be configured via PKTDMA split channel's peer registers to match
  24   with the configuration of the legacy peripheral.
  25
  26 allOf:
  27   - $ref: /schemas/dma/dma-controller.yaml#
  28
  29 properties:
  30   compatible:
  31     const: ti,am64-dmss-pktdma
  32
  33   "#dma-cells":
  34     const: 2
  35     description: |
  36       The first cell is the PSI-L  thread ID of the remote (to PKTDMA) end.
  37       Valid ranges for thread ID depends on the data movement direction:
  38       for source thread IDs (rx): 0 - 0x7fff
  39       for destination thread IDs (tx): 0x8000 - 0xffff
  40
  41       Please refer to the device documentation for the PSI-L thread map and also
  42       the PSI-L peripheral chapter for the correct thread ID.
  43
  44       The second cell is the ASEL value for the channel
  45
  46   reg:
  47     maxItems: 4
  48
  49   reg-names:
  50     items:
  51       - const: gcfg
  52       - const: rchanrt
  53       - const: tchanrt
  54       - const: ringrt
  55
  56   msi-parent: true
  57
  58   ti,sci-rm-range-tchan:
  59     $ref: /schemas/types.yaml#/definitions/uint32-array
  60     description: |
  61       Array of PKTDMA split tx channel resource subtypes for resource allocation
  62       for this host
  63     minItems: 1
  64     # Should be enough
  65     maxItems: 255
  66     items:
  67       maximum: 0x3f
  68
  69   ti,sci-rm-range-tflow:
  70     $ref: /schemas/types.yaml#/definitions/uint32-array
  71     description: |
  72       Array of PKTDMA split tx flow resource subtypes for resource allocation
  73       for this host
  74     minItems: 1
  75     # Should be enough
  76     maxItems: 255
  77     items:
  78       maximum: 0x3f
  79
  80   ti,sci-rm-range-rchan:
  81     $ref: /schemas/types.yaml#/definitions/uint32-array
  82     description: |
  83       Array of PKTDMA split rx channel resource subtypes for resource allocation
  84       for this host
  85     minItems: 1
  86     # Should be enough
  87     maxItems: 255
  88     items:
  89       maximum: 0x3f
  90
  91   ti,sci-rm-range-rflow:
  92     $ref: /schemas/types.yaml#/definitions/uint32-array
  93     description: |
  94       Array of PKTDMA split rx flow resource subtypes for resource allocation
  95       for this host
  96     minItems: 1
  97     # Should be enough
  98     maxItems: 255
  99     items:
 100       maximum: 0x3f
 101
 102 required:
 103   - compatible
 104   - "#dma-cells"
 105   - reg
 106   - reg-names
 107   - msi-parent
 108   - ti,sci
 109   - ti,sci-dev-id
 110   - ti,sci-rm-range-tchan
 111   - ti,sci-rm-range-tflow
 112   - ti,sci-rm-range-rchan
 113   - ti,sci-rm-range-rflow
 114
 115 unevaluatedProperties: false
 116
 117 examples:
 118   - |+
 119     cbass_main {
 120         #address-cells = <2>;
 121         #size-cells = <2>;
 122
 123         main_dmss {
 124             compatible = "simple-mfd";
 125             #address-cells = <2>;
 126             #size-cells = <2>;
 127             dma-ranges;
 128             ranges;
 129
 130             ti,sci-dev-id = <25>;
 131
 132             main_pktdma: dma-controller@485c0000 {
 133                 compatible = "ti,am64-dmss-pktdma";
 134
 135                 reg = <0x0 0x485c0000 0x0 0x100>,
 136                       <0x0 0x4a800000 0x0 0x20000>,
 137                       <0x0 0x4aa00000 0x0 0x40000>,
 138                       <0x0 0x4b800000 0x0 0x400000>;
 139                 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
 140                 msi-parent = <&inta_main_dmss>;
 141                 #dma-cells = <2>;
 142
 143                 ti,sci = <&dmsc>;
 144                 ti,sci-dev-id = <30>;
 145
 146                 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
 147                                         <0x24>, /* CPSW_TX_CHAN */
 148                                         <0x25>, /* SAUL_TX_0_CHAN */
 149                                         <0x26>, /* SAUL_TX_1_CHAN */
 150                                         <0x27>, /* ICSSG_0_TX_CHAN */
 151                                         <0x28>; /* ICSSG_1_TX_CHAN */
 152                 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
 153                                         <0x11>, /* RING_CPSW_TX_CHAN */
 154                                         <0x12>, /* RING_SAUL_TX_0_CHAN */
 155                                         <0x13>, /* RING_SAUL_TX_1_CHAN */
 156                                         <0x14>, /* RING_ICSSG_0_TX_CHAN */
 157                                         <0x15>; /* RING_ICSSG_1_TX_CHAN */
 158                 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
 159                                         <0x2b>, /* CPSW_RX_CHAN */
 160                                         <0x2d>, /* SAUL_RX_0_CHAN */
 161                                         <0x2f>, /* SAUL_RX_1_CHAN */
 162                                         <0x31>, /* SAUL_RX_2_CHAN */
 163                                         <0x33>, /* SAUL_RX_3_CHAN */
 164                                         <0x35>, /* ICSSG_0_RX_CHAN */
 165                                         <0x37>; /* ICSSG_1_RX_CHAN */
 166                 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
 167                                         <0x2c>, /* FLOW_CPSW_RX_CHAN */
 168                                         <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 169                                         <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
 170                                         <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
 171                                         <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
 172             };
 173         };
 174     };