1 Aspeed SGPIO controller Device Tree Bindings
2 --------------------------------------------
4 This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
5 featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
6 support the following options:
7 - Support interrupt option for each input port and various interrupt
8 sensitivity option (level-high, level-low, edge-high, edge-low)
9 - Support reset tolerance option for each output port
10 - Directly connected to APB bus and its shift clock is from APB bus clock
11 divided by a programmable value.
12 - Co-work with external signal-chained TTL components (74LV165/74LV595)
16 - compatible : Should be one of
17 "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
18 - #gpio-cells : Should be 2, see gpio.txt
19 - reg : Address and length of the register set for the device
20 - gpio-controller : Marks the device node as a GPIO controller
21 - interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
22 - interrupt-controller : Mark the GPIO controller as an interrupt-controller
23 - ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
24 2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
25 output. Up to 80 pins, must be a multiple of 8.
26 - clocks : A phandle to the APB clock for SGPM clock division
27 - bus-frequency : SGPM CLK frequency
29 The sgpio and interrupt properties are further described in their respective
30 bindings documentation:
32 - Documentation/devicetree/bindings/gpio/gpio.txt
33 - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
36 sgpio: sgpio@1e780200 {
38 compatible = "aspeed,ast2500-sgpio";
41 reg = <0x1e780200 0x0100>;
42 clocks = <&syscon ASPEED_CLK_APB>;
45 bus-frequency = <12000000>;