1 Device tree configuration for the GFX display device on the ASPEED SoCs
5 * Must be one of the following:
8 * In addition, the ASPEED pinctrl bindings require the 'syscon' property to
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
15 - clocks: clock number used to generate the pixel clock
17 - resets: reset line that must be released to use the GFX device
20 Phandle to a memory region to allocate from, as defined in
21 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
28 reg = <0x1e6e6000 0x1000>;
30 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
31 resets = <&syscon ASPEED_RESET_CRT1>;
33 memory-region = <&gfx_memory>;
36 gfx_memory: framebuffer {
38 alignment = <0x01000000>;
39 compatible = "shared-dma-pool";