WIP FPC-III support
[linux/fpc-iii.git] / Documentation / devicetree / bindings / i2c / snps,designware-i2c.yaml
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1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB I2C Controller
9 maintainers:
10   - Jarkko Nikula <jarkko.nikula@linux.intel.com>
12 allOf:
13   - $ref: /schemas/i2c/i2c-controller.yaml#
14   - if:
15       properties:
16         compatible:
17           not:
18             contains:
19               const: mscc,ocelot-i2c
20     then:
21       properties:
22         reg:
23           maxItems: 1
25 properties:
26   compatible:
27     oneOf:
28       - description: Generic Synopsys DesignWare I2C controller
29         const: snps,designware-i2c
30       - description: Microsemi Ocelot SoCs I2C controller
31         items:
32           - const: mscc,ocelot-i2c
33           - const: snps,designware-i2c
34       - description: Baikal-T1 SoC System I2C controller
35         const: baikal,bt1-sys-i2c
37   reg:
38     minItems: 1
39     items:
40       - description: DW APB I2C controller memory mapped registers
41       - description: |
42           ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
43           This registers are specific to the Ocelot I2C-controller.
45   interrupts:
46     maxItems: 1
48   clocks:
49     minItems: 1
50     items:
51       - description: I2C controller reference clock source
52       - description: APB interface clock source
54   clock-names:
55     minItems: 1
56     items:
57       - const: ref
58       - const: pclk
60   resets:
61     maxItems: 1
63   clock-frequency:
64     description: Desired I2C bus clock frequency in Hz
65     enum: [100000, 400000, 1000000, 3400000]
66     default: 400000
68   i2c-sda-hold-time-ns:
69     maxItems: 1
70     description: |
71       The property should contain the SDA hold time in nanoseconds. This option
72       is only supported in hardware blocks version 1.11a or newer or on
73       Microsemi SoCs.
75   i2c-scl-falling-time-ns:
76     maxItems: 1
77     description: |
78       The property should contain the SCL falling time in nanoseconds.
79       This value is used to compute the tLOW period.
80     default: 300
82   i2c-sda-falling-time-ns:
83     maxItems: 1
84     description: |
85       The property should contain the SDA falling time in nanoseconds.
86       This value is used to compute the tHIGH period.
87     default: 300
89   dmas:
90     items:
91       - description: TX DMA Channel
92       - description: RX DMA Channel
94   dma-names:
95     items:
96       - const: tx
97       - const: rx
99 unevaluatedProperties: false
101 required:
102   - compatible
103   - reg
104   - interrupts
106 examples:
107   - |
108     i2c@f0000 {
109       compatible = "snps,designware-i2c";
110       reg = <0xf0000 0x1000>;
111       interrupts = <11>;
112       clock-frequency = <400000>;
113     };
114   - |
115     i2c@1120000 {
116       compatible = "snps,designware-i2c";
117       reg = <0x1120000 0x1000>;
118       interrupts = <12 1>;
119       clock-frequency = <400000>;
120       i2c-sda-hold-time-ns = <300>;
121       i2c-sda-falling-time-ns = <300>;
122       i2c-scl-falling-time-ns = <300>;
123     };
124   - |
125     i2c@2000 {
126       compatible = "snps,designware-i2c";
127       reg = <0x2000 0x100>;
128       #address-cells = <1>;
129       #size-cells = <0>;
130       clock-frequency = <400000>;
131       clocks = <&i2cclk>;
132       interrupts = <0>;
134       eeprom@64 {
135         compatible = "atmel,24c02";
136         reg = <0x64>;
137       };
138     };
139   - |
140     i2c@100400 {
141       compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
142       reg = <0x100400 0x100>, <0x198 0x8>;
143       pinctrl-0 = <&i2c_pins>;
144       pinctrl-names = "default";
145       interrupts = <8>;
146       clocks = <&ahb_clk>;
147     };