1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019 Analog Devices Inc.
5 $id: http://devicetree.org/schemas/iio/adc/adi,ad7192.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices AD7192 ADC device driver
11 - Michael Hennerich <michael.hennerich@analog.com>
14 Bindings for the Analog Devices AD7192 ADC device. Datasheet can be
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7192.pdf
33 spi-max-frequency: true
37 description: phandle to the master clock (mclk)
47 description: DVdd voltage supply
50 description: AVdd voltage supply
52 adi,rejection-60-Hz-enable:
54 This bit enables a notch at 60 Hz when the first notch of the sinc
55 filter is at 50 Hz. When REJ60 is set, a filter notch is placed at
56 60 Hz when the sinc filter first notch is at 50 Hz. This allows
57 simultaneous 50 Hz/ 60 Hz rejection.
60 adi,refin2-pins-enable:
62 External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins.
67 Enables the buffer on the analog inputs. If cleared, the analog inputs
68 are unbuffered, lowering the power consumption of the device. If this
69 bit is set, the analog inputs are buffered, allowing the user to place
70 source impedances on the front end without contributing gain errors to
74 adi,burnout-currents-enable:
76 When this bit is set to 1, the 500 nA current sources in the signal
77 path are enabled. When BURN = 0, the burnout currents are disabled.
78 The burnout currents can be enabled only when the buffer is active
79 and when chop is disabled.
83 description: see Documentation/devicetree/bindings/iio/adc/adc.txt
97 additionalProperties: false
102 #address-cells = <1>;
106 compatible = "adi,ad7192";
108 spi-max-frequency = <1000000>;
111 clocks = <&ad7192_mclk>;
112 clock-names = "mclk";
113 interrupts = <25 0x2>;
114 interrupt-parent = <&gpio>;
115 dvdd-supply = <&dvdd>;
116 avdd-supply = <&avdd>;
118 adi,refin2-pins-enable;
119 adi,rejection-60-Hz-enable;
121 adi,burnout-currents-enable;