1 * TI - TSC ADC (Touschscreen and analog digital converter)
2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 "ti,am3359-tscadc" for AM335x/AM437x SoCs
8 "ti,am654-tscadc", "ti,am3359-tscadc" for AM654 SoCs
10 compatible: Should be "ti,am3359-tsc".
11 ti,wires: Wires refer to application modes i.e. 4/5/8 wire touchscreen
12 support on the platform.
13 ti,x-plate-resistance: X plate resistance
14 ti,coordinate-readouts: The sequencer supports a total of 16
15 programmable steps each step is used to
16 read a single coordinate. A single
17 readout is enough but multiple reads can
19 A value of 5 means, 5 reads for X, 5 for
20 Y and 2 for Z (always). This utilises 12
21 of the 16 software steps available. The
22 remaining 4 can be used by the ADC.
23 ti,wire-config: Different boards could have a different order for
24 connecting wires on touchscreen. We need to provide an
25 8 bit number where in the 1st four bits represent the
26 analog lines and the next 4 bits represent positive/
27 negative terminal on that input line. Notations to
28 represent the input lines and terminals resoectively
30 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7.
31 XP = 0, XN = 1, YP = 2, YN = 3.
34 "ti,am3359-adc" for AM335x/AM437x SoCs
35 "ti,am654-adc", "ti,am3359-adc" for AM654 SoCs
36 ti,adc-channels: List of analog inputs available for ADC.
37 AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7.
41 ti,charge-delay: Length of touch screen charge delay step in terms of
42 ADC clock cycles. Charge delay value should be large
43 in order to avoid false pen-up events. This value
44 effects the overall sampling speed, hence need to be
45 kept as low as possible, while avoiding false pen-up
46 event. Start from a lower value, say 0x400, and
47 increase value until false pen-up events are avoided.
48 The pen-up detection happens immediately after the
49 charge step, so this does in fact function as a
50 hardware knob for adjusting the amount of "settling
54 ti,chan-step-opendelay: List of open delays for each channel of
55 ADC in the order of ti,adc-channels. The
56 value corresponds to the number of ADC
57 clock cycles to wait after applying the
58 step configuration registers and before
59 sending the start of ADC conversion.
60 Maximum value is 0x3FFFF.
61 ti,chan-step-sampledelay: List of sample delays for each channel
62 of ADC in the order of ti,adc-channels.
63 The value corresponds to the number of
64 ADC clock cycles to sample (to hold
65 start of conversion high).
66 Maximum value is 0xFF.
67 ti,chan-step-avg: Number of averages to be performed for each
68 channel of ADC. If average is 16 then input
69 is sampled 16 times and averaged to get more
70 accurate value. This increases the time taken
71 by ADC to generate a sample. Valid range is 0
72 average to 16 averages. Maximum value is 16.
75 tscadc: tscadc@44e0d000 {
76 compatible = "ti,am3359-tscadc";
79 ti,x-plate-resistance = <200>;
80 ti,coordiante-readouts = <5>;
81 ti,wire-config = <0x00 0x11 0x22 0x33>;
82 ti,charge-delay = <0x400>;
86 ti,adc-channels = <4 5 6 7>;
87 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
88 ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>;
89 ti,chan-step-avg = <16 2 4 8>;