Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
   8
   9 maintainers:
  10   - Alexandre Belloni <alexandre.belloni@bootlin.com>
  11
  12 allOf:
  13   - $ref: /schemas/interrupt-controller.yaml#
  14
  15 description: |
  16   the Microsemi Ocelot interrupt controller that is part of the
  17   ICPU. It is connected directly to the MIPS core interrupt
  18   controller.
  19
  20 properties:
  21   compatible:
  22     items:
  23       - enum:
  24           - mscc,jaguar2-icpu-intr
  25           - mscc,luton-icpu-intr
  26           - mscc,ocelot-icpu-intr
  27           - mscc,serval-icpu-intr
  28
  29
  30   '#interrupt-cells':
  31     const: 1
  32
  33   '#address-cells':
  34     const: 0
  35
  36   interrupt-controller: true
  37
  38   reg:
  39     maxItems: 1
  40
  41   interrupts:
  42     maxItems: 1
  43
  44 required:
  45   - compatible
  46   - '#interrupt-cells'
  47   - '#address-cells'
  48   - interrupt-controller
  49   - reg
  50
  51 additionalProperties: false
  52
  53 examples:
  54   - |
  55     intc: interrupt-controller@70000070 {
  56         compatible = "mscc,ocelot-icpu-intr";
  57         reg = <0x70000070 0x70>;
  58         #interrupt-cells = <1>;
  59         #address-cells = <0>;
  60         interrupt-controller;
  61         interrupt-parent = <&cpuintc>;
  62         interrupts = <2>;
  63     };
  64 ...