1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM SMMUv3 Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 The SMMUv3 architecture is a significant departure from previous
15 revisions, replacing the MMIO register interface with in-memory command
16 and event queues and adding support for the ATS and PRI components of
17 the PCIe specification.
21 pattern: "^iommu@[0-9a-f]*"
36 The combined interrupt is optional, and should only be provided if the
37 hardware supports just a single, combined interrupt line.
38 If provided, then the combined interrupt will be used in preference to
43 - const: eventq # Event Queue not empty
44 - const: gerror # Global Error activated
45 - const: priq # PRI Queue not empty
46 - const: cmdq-sync # CMD_SYNC complete
53 Present if page table walks made by the SMMU are cache coherent with the
56 NOTE: this only applies to the SMMU itself, not masters connected
61 hisilicon,broken-prefetch-cmd:
63 description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
65 cavium,cn9900-broken-page1-regspace:
68 Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
69 register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
70 doesn't support SMMU page1 register space.
77 additionalProperties: false
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/interrupt-controller/irq.h>
85 compatible = "arm,smmu-v3";
86 reg = <0x2b400000 0x20000>;
87 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
88 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
89 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
90 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
91 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
94 msi-parent = <&its 0xff0000>;