1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner sunxi Message Box
10 - Samuel Holland <samuel@sholland.org>
13 The hardware message box on sun6i, sun8i, sun9i, and sun50i SoCs is a
14 two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
15 is raised for received messages, but software must poll to know when a
16 transmitted message has been acknowledged by the remote user. Each FIFO can
17 hold four 32-bit messages; when a FIFO is full, clients must wait before
18 attempting more transmissions.
20 Refer to ./mailbox.txt for generic information about mailbox device-tree
28 - allwinner,sun8i-a83t-msgbox
29 - allwinner,sun8i-h3-msgbox
30 - allwinner,sun9i-a80-msgbox
31 - allwinner,sun50i-a64-msgbox
32 - allwinner,sun50i-h6-msgbox
33 - const: allwinner,sun6i-a31-msgbox
34 - const: allwinner,sun6i-a31-msgbox
41 description: bus clock
45 description: bus reset
52 description: first cell is the channel number (0-7)
62 additionalProperties: false
66 #include <dt-bindings/clock/sun8i-h3-ccu.h>
67 #include <dt-bindings/interrupt-controller/arm-gic.h>
68 #include <dt-bindings/reset/sun8i-h3-ccu.h>
70 msgbox: mailbox@1c17000 {
71 compatible = "allwinner,sun8i-h3-msgbox",
72 "allwinner,sun6i-a31-msgbox";
73 reg = <0x01c17000 0x1000>;
74 clocks = <&ccu CLK_BUS_MSGBOX>;
75 resets = <&ccu RST_BUS_MSGBOX>;
76 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;