Documentation/devicetree/bindings/media/i2c/tda1997x.txt

   1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
   2
   3 The TDA19971/73 are HDMI video receivers.
   4
   5 The TDA19971 Video port output pins can be used as follows:
   6  - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
   7  - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
   8  - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
   9  - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
  10  - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
  11  - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
  12  - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
  13  - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
  14
  15 The TDA19973 Video port output pins can be used as follows:
  16  - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
  17  - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
  18  - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
  19  - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
  20
  21 The Video port output pins are mapped via 4-bit 'pin groups' allowing
  22 for a variety of connection possibilities including swapping pin order within
  23 pin groups. The video_portcfg device-tree property consists of register mapping
  24 pairs which map a chip-specific VP output register to a 4-bit pin group. If
  25 the pin group needs to be bit-swapped you can use the *_S pin-group defines.
  26
  27 Required Properties:
  28  - compatible          :
  29   - "nxp,tda19971" for the TDA19971
  30   - "nxp,tda19973" for the TDA19973
  31  - reg                 : I2C slave address
  32  - interrupts          : The interrupt number
  33  - DOVDD-supply        : Digital I/O supply
  34  - DVDD-supply         : Digital Core supply
  35  - AVDD-supply         : Analog supply
  36  - nxp,vidout-portcfg  : array of pairs mapping VP output pins to pin groups.
  37
  38 Optional Properties:
  39  - nxp,audout-format   : DAI bus format: "i2s" or "spdif".
  40  - nxp,audout-width    : width of audio output data bus (1-4).
  41  - nxp,audout-layout   : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
  42  - nxp,audout-mclk-fs  : Multiplication factor between stream rate and codec
  43                          mclk.
  44
  45 The port node shall contain one endpoint child node for its digital
  46 output video port, in accordance with the video interface bindings defined in
  47 Documentation/devicetree/bindings/media/video-interfaces.txt.
  48
  49 Optional Endpoint Properties:
  50   The following three properties are defined in video-interfaces.txt and
  51   are valid for the output parallel bus endpoint:
  52   - hsync-active: Horizontal synchronization polarity. Defaults to active high.
  53   - vsync-active: Vertical synchronization polarity. Defaults to active high.
  54   - data-active: Data polarity. Defaults to active high.
  55
  56 Examples:
  57  - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
  58    16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
  59         hdmi-receiver@48 {
  60                 compatible = "nxp,tda19971";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_tda1997x>;
  63                 reg = <0x48>;
  64                 interrupt-parent = <&gpio1>;
  65                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  66                 DOVDD-supply = <&reg_3p3v>;
  67                 AVDD-supply = <&reg_1p8v>;
  68                 DVDD-supply = <&reg_1p8v>;
  69                 /* audio */
  70                 #sound-dai-cells = <0>;
  71                 nxp,audout-format = "i2s";
  72                 nxp,audout-layout = <0>;
  73                 nxp,audout-width = <16>;
  74                 nxp,audout-mclk-fs = <128>;
  75                 /*
  76                  * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
  77                  * and Y[11:4] across 16bits in the same pixclk cycle.
  78                  */
  79                 nxp,vidout-portcfg =
  80                         /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
  81                         < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
  82                         /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
  83                         < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
  84                         /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
  85                         < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
  86                         /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
  87                         < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
  88
  89                 port {
  90                         tda1997x_to_ipu1_csi0_mux: endpoint {
  91                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  92                                 bus-width = <16>;
  93                                 hsync-active = <1>;
  94                                 vsync-active = <1>;
  95                                 data-active = <1>;
  96                         };
  97                 };
  98         };
  99  - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
 100    16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
 101         hdmi-receiver@48 {
 102                 compatible = "nxp,tda19971";
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&pinctrl_tda1997x>;
 105                 reg = <0x48>;
 106                 interrupt-parent = <&gpio1>;
 107                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 108                 DOVDD-supply = <&reg_3p3v>;
 109                 AVDD-supply = <&reg_1p8v>;
 110                 DVDD-supply = <&reg_1p8v>;
 111                 /* audio */
 112                 #sound-dai-cells = <0>;
 113                 nxp,audout-format = "i2s";
 114                 nxp,audout-layout = <0>;
 115                 nxp,audout-width = <16>;
 116                 nxp,audout-mclk-fs = <128>;
 117                 /*
 118                  * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
 119                  * and Y[11:4] across 16bits in the same pixclk cycle.
 120                  */
 121                 nxp,vidout-portcfg =
 122                         /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
 123                         < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
 124                         /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
 125                         < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
 126                         /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
 127                         < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
 128                         /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
 129                         < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
 130
 131                 port {
 132                         tda1997x_to_ipu1_csi0_mux: endpoint {
 133                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 134                                 bus-width = <16>;
 135                                 hsync-active = <1>;
 136                                 vsync-active = <1>;
 137                                 data-active = <1>;
 138                         };
 139                 };
 140         };
 141  - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
 142    16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
 143         hdmi-receiver@48 {
 144                 compatible = "nxp,tda19971";
 145                 pinctrl-names = "default";
 146                 pinctrl-0 = <&pinctrl_tda1997x>;
 147                 reg = <0x48>;
 148                 interrupt-parent = <&gpio1>;
 149                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 150                 DOVDD-supply = <&reg_3p3v>;
 151                 AVDD-supply = <&reg_1p8v>;
 152                 DVDD-supply = <&reg_1p8v>;
 153                 /* audio */
 154                 #sound-dai-cells = <0>;
 155                 nxp,audout-format = "i2s";
 156                 nxp,audout-layout = <0>;
 157                 nxp,audout-width = <16>;
 158                 nxp,audout-mclk-fs = <128>;
 159                 /*
 160                  * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
 161                  * 2 pixclk cycles.
 162                  */
 163                 nxp,vidout-portcfg =
 164                         /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
 165                         < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,
 166                         /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
 167                         < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,
 168
 169                 port {
 170                         tda1997x_to_ipu1_csi0_mux: endpoint {
 171                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 172                                 bus-width = <16>;
 173                                 hsync-active = <1>;
 174                                 vsync-active = <1>;
 175                                 data-active = <1>;
 176                         };
 177                 };
 178         };