1 * MediaTek JPEG Encoder
3 MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
6 - compatible : "mediatek,mt2701-jpgenc"
7 followed by "mediatek,mtk-jpgenc"
8 - reg : physical base address of the JPEG encoder registers and length of
10 - interrupts : interrupt number to the interrupt controller.
11 - clocks: device clocks, see
12 Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13 - clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
14 - power-domains: a phandle to the power domain, see
15 Documentation/devicetree/bindings/power/power_domain.txt for details.
16 - mediatek,larb: must contain the local arbiters in the current SoCs, see
17 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
19 - iommus: should point to the respective IOMMU block with master port as
20 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
24 jpegenc: jpegenc@1500a000 {
25 compatible = "mediatek,mt2701-jpgenc",
26 "mediatek,mtk-jpgenc";
27 reg = <0 0x1500a000 0 0x1000>;
28 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
29 clocks = <&imgsys CLK_IMG_VENC>;
30 clock-names = "jpgenc";
31 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
32 mediatek,larb = <&larb2>;
33 iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
34 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;