| blob | 498234629e218599bc24c749e6a88cd0110b5c4f |
1 Qualcomm Camera Subsystem
3 * Properties
5 - compatible:
6 Usage: required
7 Value type: <stringlist>
8 Definition: Should contain one of:
9 - "qcom,msm8916-camss"
10 - "qcom,msm8996-camss"
11 - "qcom,sdm660-camss"
12 - reg:
13 Usage: required
14 Value type: <prop-encoded-array>
15 Definition: Register ranges as listed in the reg-names property.
16 - reg-names:
17 Usage: required
18 Value type: <stringlist>
19 Definition: Should contain the following entries:
20 - "csiphy0"
21 - "csiphy0_clk_mux"
22 - "csiphy1"
23 - "csiphy1_clk_mux"
24 - "csiphy2" (8996 only)
25 - "csiphy2_clk_mux" (8996 only)
26 - "csid0"
27 - "csid1"
28 - "csid2" (8996 only)
29 - "csid3" (8996 only)
30 - "ispif"
31 - "csi_clk_mux"
32 - "vfe0"
33 - "vfe1" (8996 only)
34 - interrupts:
35 Usage: required
36 Value type: <prop-encoded-array>
37 Definition: Interrupts as listed in the interrupt-names property.
38 - interrupt-names:
39 Usage: required
40 Value type: <stringlist>
41 Definition: Should contain the following entries:
42 - "csiphy0"
43 - "csiphy1"
44 - "csiphy2" (8996 only)
45 - "csid0"
46 - "csid1"
47 - "csid2" (8996 only)
48 - "csid3" (8996 only)
49 - "ispif"
50 - "vfe0"
51 - "vfe1" (8996 only)
52 - power-domains:
53 Usage: required
54 Value type: <prop-encoded-array>
55 Definition: A phandle and power domain specifier pairs to the
56 power domain which is responsible for collapsing
57 and restoring power to the peripheral.
58 - clocks:
59 Usage: required
60 Value type: <prop-encoded-array>
61 Definition: A list of phandle and clock specifier pairs as listed
62 in clock-names property.
63 - clock-names:
64 Usage: required
65 Value type: <stringlist>
66 Definition: Should contain the following entries:
67 - "top_ahb"
68 - "throttle_axi" (660 only)
69 - "ispif_ahb"
70 - "csiphy0_timer"
71 - "csiphy1_timer"
72 - "csiphy2_timer" (8996 only)
73 - "csiphy_ahb2crif" (660 only)
74 - "csi0_ahb"
75 - "csi0"
76 - "csi0_phy"
77 - "csi0_pix"
78 - "csi0_rdi"
79 - "cphy_csid0" (660 only)
80 - "csi1_ahb"
81 - "csi1"
82 - "csi1_phy"
83 - "csi1_pix"
84 - "csi1_rdi"
85 - "cphy_csid1" (660 only)
86 - "csi2_ahb" (8996 only)
87 - "csi2" (8996 only)
88 - "csi2_phy" (8996 only)
89 - "csi2_pix" (8996 only)
90 - "csi2_rdi" (8996 only)
91 - "cphy_csid2" (660 only)
92 - "csi3_ahb" (8996 only)
93 - "csi3" (8996 only)
94 - "csi3_phy" (8996 only)
95 - "csi3_pix" (8996 only)
96 - "csi3_rdi" (8996 only)
97 - "cphy_csid3" (660 only)
98 - "ahb"
99 - "vfe0"
100 - "csi_vfe0"
101 - "vfe0_ahb", (8996 only)
102 - "vfe0_stream", (8996 only)
103 - "vfe1", (8996 only)
104 - "csi_vfe1", (8996 only)
105 - "vfe1_ahb", (8996 only)
106 - "vfe1_stream", (8996 only)
107 - "vfe_ahb"
108 - "vfe_axi"
109 - vdda-supply:
110 Usage: required
111 Value type: <phandle>
112 Definition: A phandle to voltage supply for CSI2.
113 - iommus:
114 Usage: required
115 Value type: <prop-encoded-array>
116 Definition: A list of phandle and IOMMU specifier pairs.
118 * Nodes
120 - ports:
121 Usage: required
122 Definition: As described in video-interfaces.txt in same directory.
123 Properties:
124 - reg:
125 Usage: required
126 Value type: <u32>
127 Definition: Selects CSI2 PHY interface - PHY0, PHY1
128 or PHY2 (8996 only)
129 Endpoint node properties:
130 - clock-lanes:
131 Usage: required
132 Value type: <u32>
133 Definition: The physical clock lane index. On 8916
134 the value must always be <1> as the physical
135 clock lane is lane 1. On 8996 the value must
136 always be <7> as the hardware supports D-PHY
137 and C-PHY, indexes are in a common set and
138 D-PHY physical clock lane is labeled as 7.
139 - data-lanes:
140 Usage: required
141 Value type: <prop-encoded-array>
142 Definition: An array of physical data lanes indexes.
143 Position of an entry determines the logical
144 lane number, while the value of an entry
145 indicates physical lane index. Lane swapping
146 is supported. Physical lane indexes for
147 8916: 0, 2, 3, 4; for 8996: 0, 1, 2, 3.
149 * An Example
151 camss: camss@1b00000 {
152 compatible = "qcom,msm8916-camss";
153 reg = <0x1b0ac00 0x200>,
154 <0x1b00030 0x4>,
155 <0x1b0b000 0x200>,
156 <0x1b00038 0x4>,
157 <0x1b08000 0x100>,
158 <0x1b08400 0x100>,
159 <0x1b0a000 0x500>,
160 <0x1b00020 0x10>,
161 <0x1b10000 0x1000>;
162 reg-names = "csiphy0",
163 "csiphy0_clk_mux",
164 "csiphy1",
165 "csiphy1_clk_mux",
166 "csid0",
167 "csid1",
168 "ispif",
169 "csi_clk_mux",
170 "vfe0";
171 interrupts = <GIC_SPI 78 0>,
172 <GIC_SPI 79 0>,
173 <GIC_SPI 51 0>,
174 <GIC_SPI 52 0>,
175 <GIC_SPI 55 0>,
176 <GIC_SPI 57 0>;
177 interrupt-names = "csiphy0",
178 "csiphy1",
179 "csid0",
180 "csid1",
181 "ispif",
182 "vfe0";
183 power-domains = <&gcc VFE_GDSC>;
184 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
185 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
186 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
187 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
188 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
189 <&gcc GCC_CAMSS_CSI0_CLK>,
190 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
191 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
192 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
193 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
194 <&gcc GCC_CAMSS_CSI1_CLK>,
195 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
196 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
197 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
198 <&gcc GCC_CAMSS_AHB_CLK>,
199 <&gcc GCC_CAMSS_VFE0_CLK>,
200 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
201 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
202 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
203 clock-names = "top_ahb",
204 "ispif_ahb",
205 "csiphy0_timer",
206 "csiphy1_timer",
207 "csi0_ahb",
208 "csi0",
209 "csi0_phy",
210 "csi0_pix",
211 "csi0_rdi",
212 "csi1_ahb",
213 "csi1",
214 "csi1_phy",
215 "csi1_pix",
216 "csi1_rdi",
217 "ahb",
218 "vfe0",
219 "csi_vfe0",
220 "vfe_ahb",
221 "vfe_axi";
222 vdda-supply = <&pm8916_l2>;
223 iommus = <&apps_iommu 3>;
224 ports {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 port@0 {
228 reg = <0>;
229 csiphy0_ep: endpoint {
230 clock-lanes = <1>;
231 data-lanes = <0 2>;
232 remote-endpoint = <&ov5645_ep>;
233 };
234 };
235 };
236 };