1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX8M DDR Controller
10 - Leonard Crestez <leonard.crestez@nxp.com>
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
16 It supports switching between different frequencies at runtime but during
17 this process RAM itself becomes briefly inaccessible so actual frequency
18 switching is implemented by TF-A code which runs from a SRAM area.
20 The Linux driver for the DDRC doesn't even map registers (they're included
21 for the sake of "describing hardware"), it mostly just exposes firmware
22 capabilities through standard Linux mechanism like devfreq and OPP tables.
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
49 operating-points-v2: true
58 additionalProperties: false
62 #include <dt-bindings/clock/imx8mm-clock.h>
63 ddrc: memory-controller@3d400000 {
64 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
65 reg = <0x3d400000 0x400000>;
66 clock-names = "core", "pll", "alt", "apb";
67 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
68 <&clk IMX8MM_DRAM_PLL>,
69 <&clk IMX8MM_CLK_DRAM_ALT>,
70 <&clk IMX8MM_CLK_DRAM_APB>;
71 operating-points-v2 = <&ddrc_opp_table>;