1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 PRCM Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun6i-a31-prcm
29 - allwinner,sun4i-a10-mod0-clk
30 - allwinner,sun6i-a31-apb0-clk
31 - allwinner,sun6i-a31-apb0-gates-clk
32 - allwinner,sun6i-a31-ar100-clk
33 - allwinner,sun6i-a31-clock-reset
41 const: allwinner,sun6i-a31-apb0-clk
48 # Already checked in the main schema
65 additionalProperties: false
71 const: allwinner,sun6i-a31-apb0-gates-clk
78 This additional argument passed to that clock is the
79 offset of the bit controlling this particular gate in
82 # Already checked in the main schema
100 additionalProperties: false
106 const: allwinner,sun6i-a31-ar100-clk
113 # Already checked in the main schema
119 The parent order must match the hardware programming
133 additionalProperties: false
139 const: allwinner,sun6i-a31-clock-reset
146 # Already checked in the main schema
155 additionalProperties: false
161 additionalProperties: false
165 #include <dt-bindings/clock/sun6i-a31-ccu.h>
168 compatible = "allwinner,sun6i-a31-prcm";
169 reg = <0x01f01400 0x200>;
172 compatible = "allwinner,sun6i-a31-ar100-clk";
174 clocks = <&rtc 0>, <&osc24M>,
175 <&ccu CLK_PLL_PERIPH>,
176 <&ccu CLK_PLL_PERIPH>;
177 clock-output-names = "ar100";
181 compatible = "fixed-factor-clock";
186 clock-output-names = "ahb0";
190 compatible = "allwinner,sun6i-a31-apb0-clk";
193 clock-output-names = "apb0";
196 apb0_gates: apb0_gates_clk {
197 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
200 clock-output-names = "apb0_pio", "apb0_ir",
201 "apb0_timer", "apb0_p2wi",
202 "apb0_uart", "apb0_1wire",
208 compatible = "allwinner,sun4i-a10-mod0-clk";
209 clocks = <&rtc 0>, <&osc24M>;
210 clock-output-names = "ir";
214 compatible = "allwinner,sun6i-a31-clock-reset";