3 Boards with a SoC of the Microsemi MIPS family shall have the following
7 - compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
15 functionalities: chip ID, general purpose register for software use, reset
16 controller, hardware status and configuration, efuses.
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
25 reg = <0x71070000 0x1c>;
31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
33 endianness, CPU bus control, CPU status.
36 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37 - reg : Should contain registers location and length
41 compatible = "mscc,ocelot-cpu-syscon", "syscon";
42 reg = <0x70000000 0x2c>;
47 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
48 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
49 status, SerDes muxing and a thermal sensor.
52 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
53 - reg : Should contain registers location and length
57 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
58 reg = <0x10d0000 0x10000>;