| blob | 7468d666763acf0317dce046a4ff93dc0f097bef |
1 MediaTek Gen2 PCIe controller
3 Required properties:
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 - device_type: Must be "pci"
11 - reg: Base addresses and lengths of the PCIe subsys and root ports.
12 - reg-names: Names of the above areas to use during resource lookup.
13 - #address-cells: Address representation for root ports (must be 3)
14 - #size-cells: Size representation for root ports (must be 2)
15 - clocks: Must contain an entry for each entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names:
18 Mandatory entries:
19 - sys_ckN :transaction layer and data link layer clock
20 Required entries for MT2701/MT7623:
21 - free_ck :for reference clock of PCIe subsys
22 Required entries for MT2712/MT7622:
23 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
24 initiated MMIO access
25 Required entries for MT7622:
26 - axi_ckN :application layer MMIO channel operating clock
27 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
28 pcie_mac_ck/pcie_pipe_ck is turned off
29 - obff_ckN :OBFF functional block operating clock
30 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
31 where N starting from 0 to one less than the number of root ports.
32 - phys: List of PHY specifiers (used by generic PHY framework).
33 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
34 number of PHYs as specified in *phys* property.
35 - power-domains: A phandle and power domain specifier pair to the power domain
36 which is responsible for collapsing and restoring power to the peripheral.
37 - bus-range: Range of bus numbers associated with this controller.
38 - ranges: Ranges for the PCI memory and I/O regions.
40 Required properties for MT7623/MT2701:
41 - #interrupt-cells: Size representation for interrupts (must be 1)
42 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
43 Please refer to the standard PCI bus binding document for a more detailed
44 explanation.
45 - resets: Must contain an entry for each entry in reset-names.
46 See ../reset/reset.txt for details.
47 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
48 number of root ports.
50 Required properties for MT2712/MT7622:
51 -interrupts: A list of interrupt outputs of the controller, must have one
52 entry for each PCIe port
54 In addition, the device tree node must have sub-nodes describing each
55 PCIe port interface, having the following mandatory properties:
57 Required properties:
58 - device_type: Must be "pci"
59 - reg: Only the first four bytes are used to refer to the correct bus number
60 and device number.
61 - #address-cells: Must be 3
62 - #size-cells: Must be 2
63 - #interrupt-cells: Must be 1
64 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
65 Please refer to the standard PCI bus binding document for a more detailed
66 explanation.
67 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
68 property is sufficient.
70 Examples for MT7623:
72 hifsys: syscon@1a000000 {
73 compatible = "mediatek,mt7623-hifsys",
74 "mediatek,mt2701-hifsys",
75 "syscon";
76 reg = <0 0x1a000000 0 0x1000>;
77 #clock-cells = <1>;
78 #reset-cells = <1>;
79 };
81 pcie: pcie@1a140000 {
82 compatible = "mediatek,mt7623-pcie";
83 device_type = "pci";
84 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
85 <0 0x1a142000 0 0x1000>, /* Port0 registers */
86 <0 0x1a143000 0 0x1000>, /* Port1 registers */
87 <0 0x1a144000 0 0x1000>; /* Port2 registers */
88 reg-names = "subsys", "port0", "port1", "port2";
89 #address-cells = <3>;
90 #size-cells = <2>;
91 #interrupt-cells = <1>;
92 interrupt-map-mask = <0xf800 0 0 0>;
93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
94 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
95 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
96 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
97 <&hifsys CLK_HIFSYS_PCIE0>,
98 <&hifsys CLK_HIFSYS_PCIE1>,
99 <&hifsys CLK_HIFSYS_PCIE2>;
100 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
101 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
102 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
103 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
104 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
105 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
106 <&pcie2_phy PHY_TYPE_PCIE>;
107 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
108 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
109 bus-range = <0x00 0xff>;
110 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
111 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
113 pcie@0,0 {
114 reg = <0x0000 0 0 0 0>;
115 #address-cells = <3>;
116 #size-cells = <2>;
117 #interrupt-cells = <1>;
118 interrupt-map-mask = <0 0 0 0>;
119 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
120 ranges;
121 };
123 pcie@1,0 {
124 reg = <0x0800 0 0 0 0>;
125 #address-cells = <3>;
126 #size-cells = <2>;
127 #interrupt-cells = <1>;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
130 ranges;
131 };
133 pcie@2,0 {
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 interrupt-map-mask = <0 0 0 0>;
139 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
140 ranges;
141 };
142 };
144 Examples for MT2712:
146 pcie: pcie@11700000 {
147 compatible = "mediatek,mt2712-pcie";
148 device_type = "pci";
149 reg = <0 0x11700000 0 0x1000>,
150 <0 0x112ff000 0 0x1000>;
151 reg-names = "port0", "port1";
152 #address-cells = <3>;
153 #size-cells = <2>;
154 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
157 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
158 <&pericfg CLK_PERI_PCIE0>,
159 <&pericfg CLK_PERI_PCIE1>;
160 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
161 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
162 phy-names = "pcie-phy0", "pcie-phy1";
163 bus-range = <0x00 0xff>;
164 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
166 pcie0: pcie@0,0 {
167 reg = <0x0000 0 0 0 0>;
168 #address-cells = <3>;
169 #size-cells = <2>;
170 #interrupt-cells = <1>;
171 ranges;
172 interrupt-map-mask = <0 0 0 7>;
173 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
174 <0 0 0 2 &pcie_intc0 1>,
175 <0 0 0 3 &pcie_intc0 2>,
176 <0 0 0 4 &pcie_intc0 3>;
177 pcie_intc0: interrupt-controller {
178 interrupt-controller;
179 #address-cells = <0>;
180 #interrupt-cells = <1>;
181 };
182 };
184 pcie1: pcie@1,0 {
185 reg = <0x0800 0 0 0 0>;
186 #address-cells = <3>;
187 #size-cells = <2>;
188 #interrupt-cells = <1>;
189 ranges;
190 interrupt-map-mask = <0 0 0 7>;
191 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
192 <0 0 0 2 &pcie_intc1 1>,
193 <0 0 0 3 &pcie_intc1 2>,
194 <0 0 0 4 &pcie_intc1 3>;
195 pcie_intc1: interrupt-controller {
196 interrupt-controller;
197 #address-cells = <0>;
198 #interrupt-cells = <1>;
199 };
200 };
201 };
203 Examples for MT7622:
205 pcie: pcie@1a140000 {
206 compatible = "mediatek,mt7622-pcie";
207 device_type = "pci";
208 reg = <0 0x1a140000 0 0x1000>,
209 <0 0x1a143000 0 0x1000>,
210 <0 0x1a145000 0 0x1000>;
211 reg-names = "subsys", "port0", "port1";
212 #address-cells = <3>;
213 #size-cells = <2>;
214 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
215 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
216 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
217 <&pciesys CLK_PCIE_P1_MAC_EN>,
218 <&pciesys CLK_PCIE_P0_AHB_EN>,
219 <&pciesys CLK_PCIE_P1_AHB_EN>,
220 <&pciesys CLK_PCIE_P0_AUX_EN>,
221 <&pciesys CLK_PCIE_P1_AUX_EN>,
222 <&pciesys CLK_PCIE_P0_AXI_EN>,
223 <&pciesys CLK_PCIE_P1_AXI_EN>,
224 <&pciesys CLK_PCIE_P0_OBFF_EN>,
225 <&pciesys CLK_PCIE_P1_OBFF_EN>,
226 <&pciesys CLK_PCIE_P0_PIPE_EN>,
227 <&pciesys CLK_PCIE_P1_PIPE_EN>;
228 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
229 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
230 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
231 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
232 phy-names = "pcie-phy0", "pcie-phy1";
233 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
234 bus-range = <0x00 0xff>;
235 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
237 pcie0: pcie@0,0 {
238 reg = <0x0000 0 0 0 0>;
239 #address-cells = <3>;
240 #size-cells = <2>;
241 #interrupt-cells = <1>;
242 ranges;
243 interrupt-map-mask = <0 0 0 7>;
244 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
245 <0 0 0 2 &pcie_intc0 1>,
246 <0 0 0 3 &pcie_intc0 2>,
247 <0 0 0 4 &pcie_intc0 3>;
248 pcie_intc0: interrupt-controller {
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <1>;
252 };
253 };
255 pcie1: pcie@1,0 {
256 reg = <0x0800 0 0 0 0>;
257 #address-cells = <3>;
258 #size-cells = <2>;
259 #interrupt-cells = <1>;
260 ranges;
261 interrupt-map-mask = <0 0 0 7>;
262 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
263 <0 0 0 2 &pcie_intc1 1>,
264 <0 0 0 3 &pcie_intc1 2>,
265 <0 0 0 4 &pcie_intc1 3>;
266 pcie_intc1: interrupt-controller {
267 interrupt-controller;
268 #address-cells = <0>;
269 #interrupt-cells = <1>;
270 };
271 };
272 };