Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Renesas R-Car PCIe Endpoint
   9
  10 maintainers:
  11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  12   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  13
  14 properties:
  15   compatible:
  16     items:
  17       - enum:
  18           - renesas,r8a774a1-pcie-ep     # RZ/G2M
  19           - renesas,r8a774b1-pcie-ep     # RZ/G2N
  20           - renesas,r8a774c0-pcie-ep     # RZ/G2E
  21           - renesas,r8a774e1-pcie-ep     # RZ/G2H
  22       - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
  23
  24   reg:
  25     maxItems: 5
  26
  27   reg-names:
  28     items:
  29       - const: apb-base
  30       - const: memory0
  31       - const: memory1
  32       - const: memory2
  33       - const: memory3
  34
  35   interrupts:
  36     minItems: 3
  37     maxItems: 3
  38
  39   power-domains:
  40     maxItems: 1
  41
  42   resets:
  43     maxItems: 1
  44
  45   clocks:
  46     maxItems: 1
  47
  48   clock-names:
  49     items:
  50       - const: pcie
  51
  52   max-functions:
  53     minimum: 1
  54     maximum: 1
  55
  56 required:
  57   - compatible
  58   - reg
  59   - reg-names
  60   - interrupts
  61   - resets
  62   - power-domains
  63   - clocks
  64   - clock-names
  65   - max-functions
  66
  67 additionalProperties: false
  68
  69 examples:
  70   - |
  71     #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
  72     #include <dt-bindings/interrupt-controller/arm-gic.h>
  73     #include <dt-bindings/power/r8a774c0-sysc.h>
  74
  75      pcie0_ep: pcie-ep@fe000000 {
  76             compatible = "renesas,r8a774c0-pcie-ep",
  77                          "renesas,rcar-gen3-pcie-ep";
  78             reg = <0xfe000000 0x80000>,
  79                   <0xfe100000 0x100000>,
  80                   <0xfe200000 0x200000>,
  81                   <0x30000000 0x8000000>,
  82                   <0x38000000 0x8000000>;
  83             reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
  84             interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  85                          <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  86                          <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  87             resets = <&cpg 319>;
  88             power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
  89             clocks = <&cpg CPG_MOD 319>;
  90             clock-names = "pcie";
  91             max-functions = /bits/ 8 <1>;
  92     };