1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
23 - socionext,uniphier-pxs2-usb3-ssphy
24 - socionext,uniphier-ld20-usb3-ssphy
25 - socionext,uniphier-pxs3-usb3-ssphy
28 description: PHY register region (offset and length)
39 - items: # for Pro4, Pro5
42 - items: # for PXs3 with phy-ext
55 - items: # for Pro4,Pro5
63 description: A phandle to the regulator for USB VBUS
75 additionalProperties: false
80 compatible = "socionext,uniphier-ld20-dwc3-glue",
84 ranges = <0 0x65b00000 0x400>;
86 usb_ssphy0: ss-phy@300 {
87 compatible = "socionext,uniphier-ld20-usb3-ssphy";
90 clock-names = "link", "phy";
91 clocks = <&sys_clk 14>, <&sys_clk 16>;
92 reset-names = "link", "phy";
93 resets = <&sys_rst 14>, <&sys_rst 16>;
94 vbus-supply = <&usb_vbus0>;