4 - compatible: Should be "zte,zx296718-pwm".
5 - reg: Physical base address and length of the controller's registers.
6 - clocks : The phandle and specifier referencing the controller's clocks.
7 - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
8 PCLK is for register access, while WCLK is the reference clock for
9 calculating period and duty cycles.
10 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
16 compatible = "zte,zx296718-pwm";
17 reg = <0x1439000 0x1000>;
18 clocks = <&lsp1crm LSP1_PWM_PCLK>,
19 <&lsp1crm LSP1_PWM_WCLK>;
20 clock-names = "pclk", "wclk";