Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt

   1 Qualcomm Technology Inc. Hexagon v56 Peripheral Image Loader
   2
   3 This document defines the binding for a component that loads and boots firmware
   4 on the Qualcomm Technology Inc. Hexagon v56 core.
   5
   6 - compatible:
   7         Usage: required
   8         Value type: <string>
   9         Definition: must be one of:
  10                     "qcom,qcs404-cdsp-pil",
  11                     "qcom,sdm845-adsp-pil"
  12
  13 - reg:
  14         Usage: required
  15         Value type: <prop-encoded-array>
  16         Definition: must specify the base address and size of the qdsp6ss register
  17
  18 - interrupts-extended:
  19         Usage: required
  20         Value type: <prop-encoded-array>
  21         Definition: must list the watchdog, fatal IRQs ready, handover and
  22                     stop-ack IRQs
  23
  24 - interrupt-names:
  25         Usage: required
  26         Value type: <stringlist>
  27         Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
  28
  29 - clocks:
  30         Usage: required
  31         Value type: <prop-encoded-array>
  32         Definition:  List of phandles and clock specifier pairs for the Hexagon,
  33                      per clock-names below.
  34
  35 - clock-names:
  36         Usage: required for SDM845 ADSP
  37         Value type: <stringlist>
  38         Definition: List of clock input name strings sorted in the same
  39                     order as the clocks property. Definition must have
  40                     "xo", "sway_cbcr", "lpass_ahbs_aon_cbcr",
  41                     "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"
  42                     and "qdsp6ss_core".
  43
  44 - clock-names:
  45         Usage: required for QCS404 CDSP
  46         Value type: <stringlist>
  47         Definition: List of clock input name strings sorted in the same
  48                     order as the clocks property. Definition must have
  49                     "xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave",
  50                     "q6ss_master", "q6_axim".
  51
  52 - power-domains:
  53         Usage: required
  54         Value type: <phandle>
  55         Definition: reference to cx power domain node.
  56
  57 - resets:
  58         Usage: required
  59         Value type: <phandle>
  60         Definition: reference to the list of resets for the Hexagon.
  61
  62 - reset-names:
  63         Usage: required for SDM845 ADSP
  64         Value type: <stringlist>
  65         Definition: must be "pdc_sync" and "cc_lpass"
  66
  67 - reset-names:
  68         Usage: required for QCS404 CDSP
  69         Value type: <stringlist>
  70         Definition: must be "restart"
  71
  72 - qcom,halt-regs:
  73         Usage: required
  74         Value type: <prop-encoded-array>
  75         Definition: a phandle reference to a syscon representing TCSR followed
  76                     by the offset within syscon for Hexagon halt register.
  77
  78 - memory-region:
  79         Usage: required
  80         Value type: <phandle>
  81         Definition: reference to the reserved-memory for the firmware
  82
  83 - qcom,smem-states:
  84         Usage: required
  85         Value type: <phandle>
  86         Definition: reference to the smem state for requesting the Hexagon to
  87                     shut down
  88
  89 - qcom,smem-state-names:
  90         Usage: required
  91         Value type: <stringlist>
  92         Definition: must be "stop"
  93
  94
  95 = SUBNODES
  96 The adsp node may have an subnode named "glink-edge" that describes the
  97 communication edge, channels and devices related to the Hexagon.
  98 See ../soc/qcom/qcom,glink.txt for details on how to describe these.
  99
 100 = EXAMPLE
 101 The following example describes the resources needed to boot control the
 102 ADSP, as it is found on SDM845 boards.
 103
 104         remoteproc@17300000 {
 105                 compatible = "qcom,sdm845-adsp-pil";
 106                 reg = <0x17300000 0x40c>;
 107
 108                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 109                         <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 110                         <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 111                         <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 112                         <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 113                 interrupt-names = "wdog", "fatal", "ready",
 114                         "handover", "stop-ack";
 115
 116                 clocks = <&rpmhcc RPMH_CXO_CLK>,
 117                         <&gcc GCC_LPASS_SWAY_CLK>,
 118                         <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
 119                         <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
 120                         <&lpasscc LPASS_QDSP6SS_XO_CLK>,
 121                         <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
 122                         <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
 123                 clock-names = "xo", "sway_cbcr",
 124                         "lpass_ahbs_aon_cbcr",
 125                         "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
 126                         "qdsp6ss_sleep", "qdsp6ss_core";
 127
 128                 power-domains = <&rpmhpd SDM845_CX>;
 129
 130                 resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
 131                          <&aoss_reset AOSS_CC_LPASS_RESTART>;
 132                 reset-names = "pdc_sync", "cc_lpass";
 133
 134                 qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
 135
 136                 memory-region = <&pil_adsp_mem>;
 137
 138                 qcom,smem-states = <&adsp_smp2p_out 0>;
 139                 qcom,smem-state-names = "stop";
 140         };