1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: "/schemas/spi/spi-controller.yaml#"
18 - const: fsl,imx1-cspi
19 - const: fsl,imx21-cspi
20 - const: fsl,imx27-cspi
21 - const: fsl,imx31-cspi
22 - const: fsl,imx35-cspi
23 - const: fsl,imx51-ecspi
24 - const: fsl,imx53-ecspi
38 - const: fsl,imx51-ecspi
48 - description: SoC SPI ipg clock
49 - description: SoC SPI per clock
58 - description: DMA controller phandle and request line for RX
59 - description: DMA controller phandle and request line for TX
67 $ref: /schemas/types.yaml#/definitions/uint32
69 Integer, representing the value of DRCTL, the register controlling
70 the SPI_READY handling. Note that to enable the DRCTL consideration,
71 the SPI_READY mode-flag needs to be set too.
72 Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).
82 unevaluatedProperties: false
86 #include <dt-bindings/clock/imx5-clock.h>
91 compatible = "fsl,imx51-ecspi";
92 reg = <0x70010000 0x4000>;
94 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
95 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
96 clock-names = "ipg", "per";