1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM memory mapped architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
14 ARM cores may have a memory mapped architected timer, which provides up to 8
15 frames with a physical and optional virtual timer per frame.
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
27 description: The control frame base address
38 description: The frequency of the main counter, in Hz. Should be present
39 only where necessary to work around broken firmware which does not configure
40 CNTFRQ on all CPUs to a uniform correct value. Use of this property is
41 strongly discouraged; fix your firmware unless absolutely impossible.
45 description: If present, the timer is powered through an always-on power
46 domain, therefore it never loses context.
48 arm,cpu-registers-not-fw-configured:
50 description: Firmware does not initialize any of the generic timer CPU
51 registers, which contain their architecturally-defined reset values. Only
52 supported for 32-bit systems which follow the ARMv7 architected reset
55 arm,no-tick-in-suspend:
57 description: The main counter does not tick when the system is in
58 low-power system suspend on some SoCs. This behavior does not match the
59 Architecture Reference Manual's specification that the system counter "must
60 be implemented in an always-on power domain."
65 description: A timer node has up to 8 frame sub-nodes, each with the following properties.
68 $ref: "/schemas/types.yaml#/definitions/uint32"
76 - description: physical timer irq
77 - description: virtual timer irq
83 - description: 1st view base address
84 - description: 2nd optional view base address
97 additionalProperties: false
102 compatible = "arm,armv7-timer-mem";
103 #address-cells = <1>;
105 ranges = <0 0xf0001000 0x1000>;
106 reg = <0xf0000000 0x1000>;
107 clock-frequency = <50000000>;
111 interrupts = <0 13 0x8>,
113 reg = <0x0000 0x1000>,
119 interrupts = <0 15 0x8>;
120 reg = <0x2000 0x1000>;