1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
31 - description: OTG/DRD controller interrupt
32 - description: XHCI host controller interrupt
33 - description: Device controller interrupt
34 - description: interrupt used to wake up core, e.g when usbcmd.rs is
35 cleared by xhci core, this interrupt is optional
46 enum: [host, otg, peripheral]
49 enum: [super-speed, high-speed, full-speed]
60 - const: cdns3,usb2-phy
61 - const: cdns3,usb3-phy
63 cdns,on-chip-buff-size:
65 size of memory intended as internal memory for endpoints
66 buffers expressed in KB
67 $ref: /schemas/types.yaml#/definitions/uint32
70 description: Enable resetting of PHY if Rx fail is detected
79 additionalProperties: false
83 #include <dt-bindings/interrupt-controller/arm-gic.h>
89 compatible = "cdns,usb3";
90 reg = <0x00 0x6000000 0x00 0x10000>,
91 <0x00 0x6010000 0x00 0x10000>,
92 <0x00 0x6020000 0x00 0x10000>;
93 reg-names = "otg", "xhci", "dev";
94 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "host", "peripheral", "otg";
98 maximum-speed = "super-speed";