1 # SPDX-License-Identifier: GPL-2.0
4 $id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
10 - Roger Quadros <rogerq@ti.com>
22 description: module registers
26 PM domain provider node and an args specifier containing
27 the USB device id value. See,
28 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
31 description: Clock phandles to usb2_refclk and lpm_clk
42 If present, it restricts the controller to USB2.0 mode of
43 operation. Must be present if USB3 PHY is not available
49 Should be present if USB VBUS line is connected to the
50 VBUS pin of the SoC via a 1/3 voltage divider.
56 assigned-clock-parents:
76 additionalProperties: false
80 #include <dt-bindings/soc/ti,sci_pm_domain.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
88 compatible = "ti,j721e-usb";
89 reg = <0x00 0x4104000 0x00 0x100>;
90 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
91 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
92 clock-names = "ref", "lpm";
93 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
94 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
99 compatible = "cdns,usb3";
100 reg = <0x00 0x6000000 0x00 0x10000>,
101 <0x00 0x6010000 0x00 0x10000>,
102 <0x00 0x6020000 0x00 0x10000>;
103 reg-names = "otg", "xhci", "dev";
104 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
105 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
106 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
107 interrupt-names = "host",
110 maximum-speed = "super-speed";