arch/alpha/kernel/sys_rx164.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *      linux/arch/alpha/kernel/sys_rx164.c
   4  *
   5  *      Copyright (C) 1995 David A Rusling
   6  *      Copyright (C) 1996 Jay A Estabrook
   7  *      Copyright (C) 1998, 1999 Richard Henderson
   8  *
   9  * Code supporting the RX164 (PCA56+POLARIS).
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/sched.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/dma.h>
  22 #include <asm/irq.h>
  23 #include <asm/mmu_context.h>
  24 #include <asm/io.h>
  25 #include <asm/core_polaris.h>
  26 #include <asm/tlbflush.h>
  27
  28 #include "proto.h"
  29 #include "irq_impl.h"
  30 #include "pci_impl.h"
  31 #include "machvec_impl.h"
  32
  33
  34 /* Note mask bit is true for ENABLED irqs.  */
  35 static unsigned long cached_irq_mask;
  36
  37 static inline void
  38 rx164_update_irq_hw(unsigned long mask)
  39 {
  40         volatile unsigned int *irq_mask;
  41
  42         irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74);
  43         *irq_mask = mask;
  44         mb();
  45         *irq_mask;
  46 }
  47
  48 static inline void
  49 rx164_enable_irq(struct irq_data *d)
  50 {
  51         rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
  52 }
  53
  54 static void
  55 rx164_disable_irq(struct irq_data *d)
  56 {
  57         rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
  58 }
  59
  60 static struct irq_chip rx164_irq_type = {
  61         .name           = "RX164",
  62         .irq_unmask     = rx164_enable_irq,
  63         .irq_mask       = rx164_disable_irq,
  64         .irq_mask_ack   = rx164_disable_irq,
  65 };
  66
  67 static void
  68 rx164_device_interrupt(unsigned long vector)
  69 {
  70         unsigned long pld;
  71         volatile unsigned int *dirr;
  72         long i;
  73
  74         /* Read the interrupt summary register.  On Polaris, this is
  75            the DIRR register in PCI config space (offset 0x84).  */
  76         dirr = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x84);
  77         pld = *dirr;
  78
  79         /*
  80          * Now for every possible bit set, work through them and call
  81          * the appropriate interrupt handler.
  82          */
  83         while (pld) {
  84                 i = ffz(~pld);
  85                 pld &= pld - 1; /* clear least bit set */
  86                 if (i == 20) {
  87                         isa_no_iack_sc_device_interrupt(vector);
  88                 } else {
  89                         handle_irq(16+i);
  90                 }
  91         }
  92 }
  93
  94 static void __init
  95 rx164_init_irq(void)
  96 {
  97         long i;
  98
  99         rx164_update_irq_hw(0);
 100         for (i = 16; i < 40; ++i) {
 101                 irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
 102                 irq_set_status_flags(i, IRQ_LEVEL);
 103         }
 104
 105         init_i8259a_irqs();
 106         common_init_isa_dma();
 107
 108         if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL))
 109                 pr_err("Failed to register isa-cascade interrupt\n");
 110 }
 111
 112
 113 /*
 114  * The RX164 changed its interrupt routing between pass1 and pass2...
 115  *
 116  * PASS1:
 117  *
 118  *      Slot    IDSEL   INTA    INTB    INTC    INTD
 119  *      0       6       5       10      15      20
 120  *      1       7       4       9       14      19
 121  *      2       5       3       8       13      18
 122  *      3       9       2       7       12      17
 123  *      4       10      1       6       11      16
 124  *
 125  * PASS2:
 126  *      Slot    IDSEL   INTA    INTB    INTC    INTD
 127  *      0       5       1       7       12      17
 128  *      1       6       2       8       13      18
 129  *      2       8       3       9       14      19
 130  *      3       9       4       10      15      20
 131  *      4       10      5       11      16      6
 132  *
 133  */
 134
 135 /*
 136  * IdSel
 137  *   5  32 bit PCI option slot 0
 138  *   6  64 bit PCI option slot 1
 139  *   7  PCI-ISA bridge
 140  *   7  64 bit PCI option slot 2
 141  *   9  32 bit PCI option slot 3
 142  *  10  PCI-PCI bridge
 143  *
 144  */
 145
 146 static int
 147 rx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 148 {
 149 #if 0
 150         static char irq_tab_pass1[6][5] __initdata = {
 151           /*INT   INTA  INTB  INTC   INTD */
 152           { 16+3, 16+3, 16+8, 16+13, 16+18},      /* IdSel 5,  slot 2 */
 153           { 16+5, 16+5, 16+10, 16+15, 16+20},     /* IdSel 6,  slot 0 */
 154           { 16+4, 16+4, 16+9, 16+14, 16+19},      /* IdSel 7,  slot 1 */
 155           { -1,     -1,    -1,    -1,   -1},      /* IdSel 8, PCI/ISA bridge */
 156           { 16+2, 16+2, 16+7, 16+12, 16+17},      /* IdSel 9,  slot 3 */
 157           { 16+1, 16+1, 16+6, 16+11, 16+16},      /* IdSel 10, slot 4 */
 158         };
 159 #else
 160         static char irq_tab[6][5] = {
 161           /*INT   INTA  INTB  INTC   INTD */
 162           { 16+0, 16+0, 16+6, 16+11, 16+16},      /* IdSel 5,  slot 0 */
 163           { 16+1, 16+1, 16+7, 16+12, 16+17},      /* IdSel 6,  slot 1 */
 164           { -1,     -1,    -1,    -1,   -1},      /* IdSel 7, PCI/ISA bridge */
 165           { 16+2, 16+2, 16+8, 16+13, 16+18},      /* IdSel 8,  slot 2 */
 166           { 16+3, 16+3, 16+9, 16+14, 16+19},      /* IdSel 9,  slot 3 */
 167           { 16+4, 16+4, 16+10, 16+15, 16+5},      /* IdSel 10, PCI-PCI */
 168         };
 169 #endif
 170         const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
 171
 172         /* JRP - Need to figure out how to distinguish pass1 from pass2,
 173            and use the correct table.  */
 174         return COMMON_TABLE_LOOKUP;
 175 }
 176
 177
 178 /*
 179  * The System Vector
 180  */
 181
 182 struct alpha_machine_vector rx164_mv __initmv = {
 183         .vector_name            = "RX164",
 184         DO_EV5_MMU,
 185         DO_DEFAULT_RTC,
 186         DO_POLARIS_IO,
 187         .machine_check          = polaris_machine_check,
 188         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 189         .min_io_address         = DEFAULT_IO_BASE,
 190         .min_mem_address        = DEFAULT_MEM_BASE,
 191
 192         .nr_irqs                = 40,
 193         .device_interrupt       = rx164_device_interrupt,
 194
 195         .init_arch              = polaris_init_arch,
 196         .init_irq               = rx164_init_irq,
 197         .init_rtc               = common_init_rtc,
 198         .init_pci               = common_init_pci,
 199         .kill_arch              = NULL,
 200         .pci_map_irq            = rx164_map_irq,
 201         .pci_swizzle            = common_swizzle,
 202 };
 203 ALIAS_MV(rx164)