1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
4 * Author: Rostislav Lisovy <lisovy@jablotron.cz>
7 #include "am335x-chilisom.dtsi"
10 model = "AM335x Chiliboard";
11 compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&led_gpio_pins>;
25 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
26 default-state = "keep";
27 linux,default-trigger = "heartbeat";
32 gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
33 default-state = "keep";
39 uart0_pins: pinmux_uart0_pins {
40 pinctrl-single,pins = <
41 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
42 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
46 cpsw_default: cpsw_default {
47 pinctrl-single,pins = <
49 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
50 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
51 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
52 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
53 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
54 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
55 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
56 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
60 cpsw_sleep: cpsw_sleep {
61 pinctrl-single,pins = <
62 /* Slave 1 reset value */
63 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
64 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
65 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
66 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
67 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
68 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
69 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
70 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
71 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
75 davinci_mdio_default: davinci_mdio_default {
76 pinctrl-single,pins = <
77 /* mdio_data.mdio_data */
78 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
79 /* mdio_clk.mdio_clk */
80 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
84 davinci_mdio_sleep: davinci_mdio_sleep {
85 pinctrl-single,pins = <
86 /* MDIO reset value */
87 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
88 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
92 usb1_drvvbus: usb1_drvvbus {
93 pinctrl-single,pins = <
94 AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
98 sd_pins: pinmux_sd_card {
99 pinctrl-single,pins = <
100 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0)
101 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0)
102 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0)
103 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0)
104 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0)
105 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0)
106 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
110 led_gpio_pins: led_gpio_pins {
111 pinctrl-single,pins = <
112 AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */
113 AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */
119 pinctrl-names = "default";
120 pinctrl-0 = <&uart0_pins>;
126 regulator-min-microvolt = <3300000>;
127 regulator-max-microvolt = <3300000>;
133 pinctrl-names = "default", "sleep";
134 pinctrl-0 = <&cpsw_default>;
135 pinctrl-1 = <&cpsw_sleep>;
140 pinctrl-names = "default", "sleep";
141 pinctrl-0 = <&davinci_mdio_default>;
142 pinctrl-1 = <&davinci_mdio_sleep>;
145 ethphy0: ethernet-phy@0 {
151 phy-handle = <ðphy0>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&usb1_drvvbus>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&sd_pins>;
166 vmmc-supply = <&ldo4_reg>;
168 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
173 interrupt-parent = <&intc>;
174 interrupts = <7>; /* NNMI */