| blob | 0b8c2a64b36f949b7963aba394f5eabf4fcb216d |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
11 *
12 * This file contains the definitions that are common to the Armada
13 * 370 and Armada XP SoC.
14 */
16 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
18 / {
19 model = "Marvell Armada 370 and XP SoC";
20 compatible = "marvell,armada-370-xp";
22 aliases {
23 serial0 = &uart0;
24 serial1 = &uart1;
25 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30 cpu@0 {
31 compatible = "marvell,sheeva-v7";
32 device_type = "cpu";
33 reg = <0>;
34 };
35 };
37 pmu {
38 compatible = "arm,cortex-a9-pmu";
39 interrupts-extended = <&mpic 3>;
40 };
42 soc {
43 #address-cells = <2>;
44 #size-cells = <1>;
45 controller = <&mbusc>;
46 interrupt-parent = <&mpic>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 clocks = <&coreclk 0>;
57 status = "disabled";
58 };
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 clocks = <&coreclk 0>;
67 status = "disabled";
68 };
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 #address-cells = <1>;
75 #size-cells = <1>;
76 clocks = <&coreclk 0>;
77 status = "disabled";
78 };
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 clocks = <&coreclk 0>;
87 status = "disabled";
88 };
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 clocks = <&coreclk 0>;
97 status = "disabled";
98 };
100 internal-regs {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
106 rtc: rtc@10300 {
107 compatible = "marvell,orion-rtc";
108 reg = <0x10300 0x20>;
109 interrupts = <50>;
110 };
112 i2c0: i2c@11000 {
113 compatible = "marvell,mv64xxx-i2c";
114 #address-cells = <1>;
115 #size-cells = <0>;
116 interrupts = <31>;
117 clocks = <&coreclk 0>;
118 status = "disabled";
119 };
121 i2c1: i2c@11100 {
122 compatible = "marvell,mv64xxx-i2c";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 interrupts = <32>;
126 clocks = <&coreclk 0>;
127 status = "disabled";
128 };
130 uart0: serial@12000 {
131 compatible = "snps,dw-apb-uart";
132 reg = <0x12000 0x100>;
133 reg-shift = <2>;
134 interrupts = <41>;
135 reg-io-width = <1>;
136 clocks = <&coreclk 0>;
137 status = "disabled";
138 };
140 uart1: serial@12100 {
141 compatible = "snps,dw-apb-uart";
142 reg = <0x12100 0x100>;
143 reg-shift = <2>;
144 interrupts = <42>;
145 reg-io-width = <1>;
146 clocks = <&coreclk 0>;
147 status = "disabled";
148 };
150 pinctrl: pin-ctrl@18000 {
151 reg = <0x18000 0x38>;
152 };
154 coredivclk: corediv-clock@18740 {
155 compatible = "marvell,armada-370-corediv-clock";
156 reg = <0x18740 0xc>;
157 #clock-cells = <1>;
158 clocks = <&mainpll>;
159 clock-output-names = "nand";
160 };
162 mbusc: mbus-controller@20000 {
163 compatible = "marvell,mbus-controller";
164 reg = <0x20000 0x100>, <0x20180 0x20>,
165 <0x20250 0x8>;
166 };
168 mpic: interrupt-controller@20a00 {
169 compatible = "marvell,mpic";
170 #interrupt-cells = <1>;
171 #size-cells = <1>;
172 interrupt-controller;
173 msi-controller;
174 };
176 coherencyfab: coherency-fabric@20200 {
177 compatible = "marvell,coherency-fabric";
178 reg = <0x20200 0xb0>, <0x21010 0x1c>;
179 };
181 timer: timer@20300 {
182 reg = <0x20300 0x30>, <0x21040 0x30>;
183 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
184 };
186 watchdog: watchdog@20300 {
187 reg = <0x20300 0x34>, <0x20704 0x4>;
188 };
190 cpurst: cpurst@20800 {
191 compatible = "marvell,armada-370-cpu-reset";
192 reg = <0x20800 0x8>;
193 };
195 pmsu: pmsu@22000 {
196 compatible = "marvell,armada-370-pmsu";
197 reg = <0x22000 0x1000>;
198 };
200 usb0: usb@50000 {
201 compatible = "marvell,orion-ehci";
202 reg = <0x50000 0x500>;
203 interrupts = <45>;
204 status = "disabled";
205 };
207 usb1: usb@51000 {
208 compatible = "marvell,orion-ehci";
209 reg = <0x51000 0x500>;
210 interrupts = <46>;
211 status = "disabled";
212 };
214 eth0: ethernet@70000 {
215 reg = <0x70000 0x4000>;
216 interrupts = <8>;
217 clocks = <&gateclk 4>;
218 status = "disabled";
219 };
221 mdio: mdio@72004 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "marvell,orion-mdio";
225 reg = <0x72004 0x4>;
226 clocks = <&gateclk 4>;
227 };
229 eth1: ethernet@74000 {
230 reg = <0x74000 0x4000>;
231 interrupts = <10>;
232 clocks = <&gateclk 3>;
233 status = "disabled";
234 };
236 sata: sata@a0000 {
237 compatible = "marvell,armada-370-sata";
238 reg = <0xa0000 0x5000>;
239 interrupts = <55>;
240 clocks = <&gateclk 15>, <&gateclk 30>;
241 clock-names = "0", "1";
242 status = "disabled";
243 };
245 nand_controller: nand-controller@d0000 {
246 compatible = "marvell,armada370-nand-controller";
247 reg = <0xd0000 0x54>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 interrupts = <113>;
251 clocks = <&coredivclk 0>;
252 status = "disabled";
253 };
255 sdio: mvsdio@d4000 {
256 compatible = "marvell,orion-sdio";
257 reg = <0xd4000 0x200>;
258 interrupts = <54>;
259 clocks = <&gateclk 17>;
260 bus-width = <4>;
261 cap-sdio-irq;
262 cap-sd-highspeed;
263 cap-mmc-highspeed;
264 status = "disabled";
265 };
266 };
268 spi0: spi@10600 {
269 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
270 <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
271 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
272 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
273 <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
274 <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
275 <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
276 <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
277 <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
278 #address-cells = <1>;
279 #size-cells = <0>;
280 cell-index = <0>;
281 interrupts = <30>;
282 clocks = <&coreclk 0>;
283 status = "disabled";
284 };
286 spi1: spi@10680 {
287 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
288 <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
289 <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
290 <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
291 <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
292 <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
293 <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
294 <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
295 <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
296 #address-cells = <1>;
297 #size-cells = <0>;
298 cell-index = <1>;
299 interrupts = <92>;
300 clocks = <&coreclk 0>;
301 status = "disabled";
302 };
303 };
305 clocks {
306 /* 2 GHz fixed main PLL */
307 mainpll: mainpll {
308 compatible = "fixed-clock";
309 #clock-cells = <0>;
310 clock-frequency = <2000000000>;
311 };
312 };
313 };